Anand Bulusu

Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region

In this paper a two dimensional analytical model of channel potential and electric field for an asymmetric and symmetric double gate three-terminal (3T) and four-terminal (4T) silicon n-tunnel field effect transistor (Si-nTFET) device in sub-threshold region, without surface accumulation or inversion, is presented. Since the modeling has been done in subthreshlod regime operation, no Quantum Mechanical (QM) study has been taken. A very good agreement of analytically modeled results with the TCAD simulated results for the three-terminal (3T) and four-terminal (4T) Si-nTFET device was found. The model presented is based on the physics of the device. The modeling is for a 3T/4T asymmetric Tunnel FET and with appropriate changes in the device parameters we can also model for symmetric devices as well. The modeling scheme is thus quite robust.

Compact model for vertical silicon nanowire based device simulation and circuit design

Verilog-A based unified compact model of silicon vertical nanowire FET is developed for circuit simulation, which includes: short channel, velocity saturation, mobility degradation, quantum mechanical effects and device parasitic. We include scalable TCAD calibrated parasitic resistance and capacitance models, which also consider device asymmetry due to vertical nanowire structure. The model shows excellent match with calibrated TCAD at device as well as circuit level for both long and short channel devices. Further, the model results underline the importance of parasitics on nanowire based circuit performance.

Nitrogen-Terminated Semiconducting Zigzag GNR FET With Negative Differential Resistance

We investigate the effects of nitrogen passivation on band structure and density of states in zigzag graphene nanoribbon (zzGNR) using first principle quantum mechanical simulations. The results show that nitrogen edge termination of zzGNR produces a bandgap (~0.7eV) around the Fermi level. We analyze the Bloch functions and projected density of states for understanding the origin of the bandgap. Based on these findings, we propose a nitrogen-passivated zzGNR FET structure having n-type electrodes and p-type scattering region using nitrogen and boron doping, respectively. We simulate and analyze its current-voltage (I-V ) characteristics using DFT combined with NEGF formalism and device density of states (DDOS). We observe a new negative differential resistance phenomenon in GNR FET, which can be controlled by the variation of the potential applied at gate of the zzGNR FET. This device has potential applications in logic, high frequency, and memory devices.

A Parallel Device Simulator Based on Finite Element Method

As semiconductor industry advances toward nano-scale technology, it comes across many issues (such as short channel, narrow width, hot-electron effects etc.), which need to be addressed in time to continue advancements with Moores Law. Technology Computer Aided Design provides a huge scope to build an environment which can be used to design and develop future devices, and study their alterations with much ease. In this paper, a parallel 2D/3D framework is presented to simulate semiconductor devices using finite element method. This method is used to discretize essential device equations and later these equations are analyzed by using a suitable methodology to find solution. OpenMP directives are used to parallelize the solution of device equations on many-core processors. To showcase the effectiveness of the method, a pn junction diode and a MOS capacitor are simulated, and the results are validated with TCAD device simulator Sentaurus.

Lateral silicon nanowire based standard cell design for higher performance

At deep nano-scale nodes Silicon Nanowire field effect transistor (SiNW FET) imparts best performance. However, analysis of SiNW FET based circuit design is lacking in existing literature. In this study, we design a standard cell library for advanced 10nm lateral SiNW FET technology in super threshold regime. For this, we create a Verilog-A compact model. Our compact Verilog-A model includes all the short channel effect as well as the geometrical dependent parasitics, which are crucial for short channel devices. The model is well calibrated with TCAD and reported fabricated data. The standard cell library developed comprise INVERTER, NAND, and NOR gate cells. Finally, we compared the standard cell performance to FinFET based standard cell. We found that the Si NW CMOS based standard cells have ∼3–4X, ∼2–3X, and 3X performance in terms of power dissipation, energy-delay product and power delay product respectively compared to FinFET based designs.

Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits

Strain engineering and inverse narrow width effect (INWE) are among the main causes of layout-dependent variations in narrow width devices. Transistor sizing and layout without considering these effects at a prelayout stage may result in suboptimal design and design/layout iterations. In this paper, we model the channel stress variations in multifinger gate structure (MFGS) empirically using 3-D technology computer aided design simulations. Thereafter, we use these stress models along with a model for INWE to establish a physics-based relationship between effective drive current and number of fingers in MFGS. We also design single-stage combinational standard cells and predict the values of their logical effort using our approach. The performance of the standard cells using our approach improves significantly compared with the conventional approach. Inverter chains (buffers) are representative and extensively used multistage circuits. Using our model of effective drive current, we propose a methodology to optimize the buffer designed and layout to maximize performance in stress-enabled technologies. We observe that the proposed methodology results in a significant reduction in power dissipation up to 35% and reduction in silicon area up to 43% as compared with the existing methodologies.

Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance

In sub 10 nm technology node, vertical silicon nanowire (VNW) FET device has become a promising substitute due to its better gate controllability, short channel immunity, high ION/IOFF ratio and CMOS compatibility. This paper presents, a standard cell library using physics based Verilog-A compact model for 10 nm vertical SiNW FET device. A unified compact model included all the nanoscale effects (e.g. short channel effects, mobility degradation, velocity saturations etc.) as well as the parasitic capacitance and resistance model, which are highly dominant in lower technology nodes. The compact model is well matched with TCAD simulation data at 10 nm VNW FET device level. The cell library builds comprises of INVERTER, NAND, NOR and Ex-OR gate cells. Further, we compared the 10 nm VNW FET based standard cell performance to 45 nm bulk CMOS based standard cell library. It is found that the VNWFET based cells library design have an advantage of delay by ~4X and power consumption by ~14X against the 45 nm CMOS technology.

Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

For sub-20-nm FinFET and nanowire (NW) complementary metal-oxide semiconductor (CMOS) devices, negative bias temperature instability (NBTI) is an important reliability issue and requires an accurate model to predict device and circuit performance. In this paper, we report a well-calibrated predictive and scalable compact Verilog-A-based compact model, integrated with an NBTI model for NW CMOS circuit simulation and design. The stress and recovery NBTI model for an Si NW field-effect transistor is obtained from experimental NW pMOSFETs using a range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar metal-oxide semiconductor field-effect transistors. This is attributed to its cylindrical gate structure, resulting in enhanced 2-D hydrogen diffusion and stress-induced Si/SiO2 traps. This emphasizes the need to evaluate NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: an inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, the interface states generation, inverter delay, and RO frequency degrade rapidly and saturate over the long-term 10-year lifetime. Finally, the design of the SRAM cell employing the multiwire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using the appropriate design configuration. This paper underscores the need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at the device and circuit level.

A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation

This paper presents a unified Verilog-A compact model for lateral silicon nanowire field effect transistor (SiNW FET). The model incorporates all nanoscale effects including short channel effects, velocity saturation, mobility degradation, and quantization. Importantly, the model includes geometry dependent, TCAD calibrated, scalable parasitic capacitances and parasitic resistance models, which are dominant at highly scaled dimension. The model is well calibrated to generate the TCAD I-V and C-V characteristics for single and multiwire long, short channel devices. In addition, the model also reproduces I-V characteristics of the reported fabricated devices by different groups to a good accuracy, which underscores the accuracy of the model. Further using the compact model, the static and dynamic analysis of CMOS inverter with 15nm gate length is presented, which match well with TCAD simulations. Using this model the impact of device parasitic on circuit performance is studied by varying device extension length. The model is able to well predict the parasitic components for circuit performance, and is an important tool for design of NW based analog and digital circuits such as differential amplifier, current mirror, cell library and SRAM. The developed model is highly time efficient than TCAD simulator for NW based circuit simulations.

A novel energy-efficient self-correcting methodology employing INWE

Operating VLSI circuits at near/sub-threshold region is emerging as the most important technique for low power applications. However, due to the increasing variability in sub-threshold regime, system performance and yield is at stake. Therefore, improved circuit techniques are needed with low power overhead which can essentially improve the yield. This paper presents a timing error Self Correcting Flip-Flop (SCFF) operating at near threshold voltage. The proposed SCFF automatically corrects timing faults in sequential elements and datapaths, thereby reducing performance degradation due to variations and improves yield. The proposed technique uses Inverse Narrow Width effect (INWE) for performance optimization. The proposed methodology is evaluated by considering few custom circuits along the data-path. The simulation results show that the proposed SCFF design achieves better yield ratio for a given frequency specification, ~0.33 at 0.4v and ~0.32 at 0.35v supply voltage against existing error detection and correction methods.