Eric Bohannon

Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise

Signal integrity has become a major problem in digital IC design. One cause is device scaling that results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. This paper introduces both a novel on-chip decoupling capacitance methodology and active noise cancellation (ANC) structure. The decoupling methodology focuses on quantification and location. The ANC structure, with an area of 50 ¿m × 55 ¿m, uses decoupling capacitance to sense noise and inject a proportional current into VSS as a method of reduction. A chip has been designed and fabricated using TSMCs 90-nm technology. Measurements show that the decoupling methodology improved the average voltage headroom loss by 17% while the ANC structure improved the average voltage headroom loss by 18%.

Analog IC Design in Ultra-Thin Oxide CMOS Technologies With Significant Direct Tunneling-Induced Gate Current

Recent studies have shown that manufacturing costs and design complexities may delay the widespread use of high-κ/metal gate nanoscale CMOS technologies. This implies that traditional (non-high-κ/non-metal gate) ultra-thin oxide technologies will remain active due to economic factors for longer periods of time. Direct tunneling is a significant source of MOSFET gate current in these technologies. Its presence fundamentally alters MOSFET functionality by invalidating the simplifying design assumption of infinite gate resistance. Analog circuit solutions to its problems do not exist in the literature. This paper proposes design solutions that attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional ultra-thin oxide CMOS technologies. The proposed solutions re quire only ultra-thin oxide devices and are investigated in a 65-nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm.

Investigating the BJT-like behavior of MOSFETs in ultra-deep-submicron CMOS technologies with significant gate current

As CMOS has moved into the nanoscale regime, direct tunneling of carriers through the thin gate oxide has resulted in non-negligible gate current. This current increases exponentially with decreasing oxide thickness, fundamentally changing MOSFET operation in the process. These changes invalidate the widely held assumption of infinite low frequency input impedance and result in MOSFETs operating similar to BJTs [1]. From a design standpoint, this modifies how CMOS circuits are analyzed and motivates a need for understanding the BJT-like behavior of MOSFETs. This work investigates this behavior in a 65 nm CMOS technology with a VDD of 1 V and equivalent oxide thickness of 1.25 nm.

An ultra-thin oxide sub-1 V CMOS bandgap voltage reference

This paper presents a sub-1 V CMOS bandgap voltage reference that accounts for the presence of direct tunneling-induced gate current. This current increases exponentially with decreasing oxide thickness and is especially prevalent in traditional non-high-i¾?/metal gate ultra-thin oxide CMOS technologies tox<3 nm, where it invalidates the simplifying design assumption of infinite gate resistance. The developed reference average temperature coefficient, TC_AVG, of 22.5 ppm/i¾?C overcomes direct tunneling by employing circuit techniques that minimize, balance, and cancel its effects. It is compared to a thick-oxide voltage reference TC_AVG=14.0 ppm/i¾?C as a means of demonstrating that ultra-thin oxide MOSFETs can achieve performance similar to that of more expensive thicker oxide MOSFETs and that they can be used to design the analog component of a mixed-signal system. The reference was investigated in a 65 nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm. Copyright

On-device STDP and synaptic normalization for neuromemristive spiking neural network

Spiking Neural Networks offer low precision communication, robustness, and low power consumption and are attractive for autonomous applications. One of the well accepted learning rules for these networks is spike time dependent plasticity which is governed by the pre- and postsynaptic spike timings. To stabilize the plasticity and avoid saturation in these learning rules, synaptic normalization is used. In this work, we propose a circuit to efficiently realize synaptic normalization in a neuromemristive system and show how it improves the plasticity for unsupervised on-device learning. High-level modeling shows the efficacy of synaptic normalization in pattern recognition and feature extraction.