Anand N. Iyer

ILD0 CMP: Technology enabler for high K metal gate in high performance logic devices

The extension of Moores Law at the 45/32nm nodes is made possible by the introduction of high-k metal gate. In the gate-last scheme to integrate high-k metal gate, planarization and surface topography control have been reported as some of the biggest process challenges. This paper presents a three-platen chemical mechanical planarization process in which fixed abrasive is used on platen 2 and a non-selective slurry is used on platen 3 with a FullVision™ in-situ endpoint system. Superior planarization and dishing performance by the fixed abrasive and consistent endpoint control by FullVision enabled tight control of within wafer, within die and wafer-to-wafer thickness variations that is critical to the success of high k metal gate in high performance logic devices.