Garlen C. Leung

Scalability enhancement of FG NAND by FG shape modification

Floating Gate (FG) NAND scaling has been severely challenged by the reduction of gate coupling ratio (CR) and increase in FG interference (FGI) below 30nm node. Firstly, scalability of inverted ‘T’ shaped FG is evaluated by 3D electrostatics simulation. It is shown that coupling ratio (CR) and Floating Gate Interference (FGI) performance can be maintained at the level of 34nm technology down to 13nm node by engineering key aspects of the FG shape namely FG top width (FGW) and effective field height (EFH) in addition to conventional scaling approaches of IPD thinning and spacer к reduction. Secondly, FG shaping is demonstrated down to FGW of 3nm and EFH of 5nm using a sacrificial oxidation technology with no birds beak to demonstrate fabrication feasibility.

ILD0 CMP: Technology enabler for high K metal gate in high performance logic devices

The extension of Moores Law at the 45/32nm nodes is made possible by the introduction of high-k metal gate. In the gate-last scheme to integrate high-k metal gate, planarization and surface topography control have been reported as some of the biggest process challenges. This paper presents a three-platen chemical mechanical planarization process in which fixed abrasive is used on platen 2 and a non-selective slurry is used on platen 3 with a FullVision™ in-situ endpoint system. Superior planarization and dishing performance by the fixed abrasive and consistent endpoint control by FullVision enabled tight control of within wafer, within die and wafer-to-wafer thickness variations that is critical to the success of high k metal gate in high performance logic devices.