Oliver Soffke

CONAN - a design exploration framework for reliable nano-electronics architectures

In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our approach is a generic (parametrical) architectural template. Configurable nanostructures for reliable nano electronics (CONAN), which embeds support for reliability at various levels of abstractions. Some of the main reliability sources are regular and decentralized structures based on simple basic computation cells designed to be robust against disturbances and noise, fault tolerance based on hardware, time and information redundancy applied at the basic cell level as well as at higher levels, self diagnosis assisted by the dynamic reconfiguration of basic computation cells and interconnect rerouting. Within the CONAN template, both technology dependent and independent models co-exists such that the more abstract layers are technology independent while the lower levels can be retargeted to various fabrication technologies. Our proposal is application-oriented and allows the designers to deal with unpredictability, and low reliability, which are unavoidable characteristics of future emerging nano-devices. When combined with the underlying software, the tools supporting the CONAN approach allow the designer to check whether the design constraints are fulfilled before performing a detailed implementation and provides means to trade area, delay, and power consumptions for reliability. As such, this proposal is a call-to-arms to mobilize the efforts of systems designers in order to achieve a systematic design methodology for reliable systems.

A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits

In this paper we present a method which allows the statistical analysis of nanoelectronic Boolean networks with respect to timing uncertainty and noise. All signals are considered to be instationary random processes which is the most general signal representation. As one cannot deal with random processes per se, we focus on certain statistical properties which are propagated through networks of Boolean gates yielding the instationary probability density function (pdf) of each signal in the network. Finally, several values of interest as the error probability, the average path delay or the average signal trace over time can be extracted from these pdf

IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter

In this paper we describe a parameterizable FPGA-based implementation of a sigma-delta converter used in a 96kHz audio DAC. From specifications of the converter’s input bitwidth and data sampling frequency, VHDL generic parameters are used to automatically generate the required design. The resulting implementation is optimized to use the minimum internal wordlength and number of stages. We prototyped the converter on an FPGA board for verification purposes and the results are presented.

UbiComp device for a decentralized distributed computing environment

This paper describes an approach for computing in ubiquitous computing environment. In a classical mobile computing environment, several data such as audio, video, text etc. are processed centrally within the mobile computing device. This centralized computing paradigm needs a dedicated processing units like signal processor, CPU etc. which occupy most of the area inside the chip and also consume significant amount of power. To scale down the problem of size and power consumption, the idea that we propose is the decentralized distributed computing environment. It consists of several distributed computing devices which are located in a pico cell. These devices do the computation like signal processing and deliver their results to either what we call a small UbiComp device (UCD) that is carried by the user or to the network. The UCD itself consists of some minor but important computation units to deliver the good QoS.

A hardware-in-the-loop system to evaluate the performance of small-world cellular automata

This paper presents the realisation of a hardware-in-the-loop system to investigate the performance of different cellular automata (CA) structures. The system is applied to regular lattice CAs and to small-world CAs, which are expected to expose better characteristics than lattice automata due to their nature-inspired structure. CA functionality is evolved using a genetic algorithm (GA) implemented as a distributed Java program running on a host computer. The performance evaluation of whole generations of individual automata is transferred to a specialised hardware architecture on an FPGA-board in order to speed up this process. For this, a customisable version of an automaton is residing on the board and personalisation data can be downloaded to it. The objective of the approach is to gather qualitative and quantitative data on the differences between the two types of CAs. We discuss two CA implementations, one of a lattice CA and one of a small-world CA. Their properties are characterised and their integration into the overall evaluation system is described.

Programmable and reconfigurable hardware architectures for the rapid prototyping of cellular automata

In this paper we describe and compare several architectures of cellular automata to be used as hardware accelerators in the evaluation loop of a genetic algorithm. In addition, two dynamically reconfigurable cell interconnection networks are presented capable to realize nonregular lattices. Cellular automata are basic computational structures of interacting units which may expose self-organization and emergent behaviour. To investigate this behaviour subject to different cell interconnect patterns, an automated inspection flow is needed, including a very fast evaluation of single specimen. For that purpose, a flexible FPGA-based accelerator for cellular automata evaluation is used, which can be accessed transparently by a Java client running the genetic algorithm. Several architectures have been developed for that: a straightforward implementation of the cellular automaton, an area-reduced architecture, a dynamically reconfigurable interconnection network, which allows the interconnection of single cells under certain constraints and, finally, a dynamically reconfigurable interconnection network, which allows to connect cells arbitrarily.