Harald Godon

The use of TiSi/sub 2/ local interconnect as an effective contact etch barrier

TiSi/sub 2/ local interconnect was used as an overetch barrier layer for shallow submicron contacts in a fully planarized submicron salicide CMOS process used for manufacturing 1-Mb SRAMs. By placing a pad of local interconnect under all contacts to polysilicon, the complete removal of the silicide is prevented. The result is a stable, low contact resistance to polysilicon.<<ETX>>

A double level metallization system having 2 mu m pitch for both levels

A double-layer metal (DLM) process having 2- mu m pitch for both metal levels has been successfully developed. This DLM system has been used in a 0.7- mu m CMOS process to fabricate 1-M SRAM and 256 K SRAM devices. Some relevant design rules are 1- mu m metal line and space for both levels, and 0.9- mu m contact and via openings. To meet these requirements, the process features planarization to minimize topology at LOCOS, polysilicon, and metal levels. The technological results are presented as well as reliability and electrical results. Photographs of fully processed and functional 256 K and 1-M high-performance SRAMs are shown.<<ETX>>

A 1M SRAM with full CMOS cells fabricated in a 0.7&#181;m technology

A high performance CMOS technology has been developed for application in very fast circuits. A 1 Mb SRAM with 6 transistor cells was designed /1/ end processed. Figure 1 shows a photograph of the completed chip. The insert is a magnification of the corresponding corner. In table 1 the most important design rules are listed with a summary of the technology and some data of the memory. The technology contains 0. 7 µm lithographic dimensions. Important features are: tight field isolation (1.0 µm) achieved by a special masking and oxidation procedure /2/, twin retrograde wells to provide high parasitic threshold and punch throughout voltages and an extremely small n+ to p+ spacing of 2. 5 µm. Latch-up is sufficiently suppressed by the use of thin p-/p+ epi material. The gate oxide thickness is 17.5 nm. Both n-channel and p-channel MOSTs contain an LDD structure. A strap technology is used to realize buried contacts and local interconnect. Ti salicide technology and double level metal offer a low resistance interconnect. Planarization is applied throughout the process.