Paolo Pellati

Radiation effects on floating-gate memory cells

We have addressed the problem of threshold voltage (V/sub TH/) variation in flash memory cells after heavy-ion irradiation by using specially designed array structures and test instruments. After irradiation, low V/sub TH/ tails appear in V/sub TH/ distributions, growing with ion linear energy transfer (LET) and fluence. In particular, high LET ions, such as iodine used in this paper, can produce a bit flip. Since the existing models cannot account for large charge losses from the floating gate, we propose a new mechanism, based on the excess of positive charge produced by a single ion, temporarily lowering the tunnel oxide barrier (positive charge assisted leakage current) and enhancing the tunneling current. This mechanism fully explains the experimental data we present.

Overerase phenomena: an insight into flash memory reliability

The most important reliability issues related to the erasing operation in flash memories are, still today, caused by single bit failures. In particular, the overerase of tail and fast bits affects the threshold voltage distribution width, causing bit-line leakage that produces read/verify circuitry malfunctions, affects the programming efficiency due to voltage drop, and causes charge-pump circuitry failure. This brief overview explores the most important characteristics of these anomalous bits, their relation with the erratic erase phenomena and their impact on flash memory reliability. Identification techniques, experimental results, and physical models are also discussed.

Automated test equipment for research on nonvolatile memories

This paper presents a measurement system for research on nonvolatile memories, such as flash, EPROM, EEPROM. The instrument architecture is based on the PCI local bus, thus allowing a direct interface of the memory under test with the PC controlling the measurement. A rank of programmable waveform generators allows applying arbitrary signals to the memory cells during writing and reading, thus guaranteeing the flexibility required at the research level. The instrument performances have been evaluated on 4 MB test chips and results are comparable to those of commercial automated test equipment (ATE). This instrument, besides the analysis of writing operations, can be successfully used to evaluate the evolution of such operations during memory cycling and their impact on long-term reliability.

Analysis of erratic bits in flash memories

This work presents experimental results concerning erratic behaviors in flash memories obtained by tracking the threshold voltage dynamics during any single erase operation and providing a deeper insight into their physical nature. The particular shape of the experimental erase curves allows the derivation of a nearly linear relationship between the amplitude of erratic threshold shifts and the equivalent barrier height controlling Fowler-Nordheim injection.

Constant charge erasing scheme for flash memories

This paper presents a new erasing scheme for flash memories based on a sequence of bulk to gate-box pulses with increasing voltage amplitude. It is experimentally and analytically demonstrated that the erasing dynamics always reaches an equilibrium condition where each pulse induces a constant and controllable injected charge and, therefore, constant threshold shifts. The analytical study allows us to express both the final threshold voltage and the oxide electric field as a function of technological, physical, and electrical parameters. Electrical parameters can be conveniently adapted to control both the threshold voltage and the oxide fields, thus reducing oxide stresses. Advantages with respect to the standard box erasing scheme are theoretically and experimentally demonstrated.

Erratic Bits in Flash Memories under Fowler-Nordheim Programming

This work demonstrates the existence of erratic bits in Flash memories also after Fowler Nordheim programming, i.e. injecting electrons into the floating gate from the channel. Experimental data and statistics allow the evaluation of the consistency of erratic erase physical models adding some useful indications about the influence of the injecting interface morphology on the erratic erase phenomenon.

Automated characterization of TAS-MRAM test arrays

In this work the characterization results of 1kbit TAS-MRAM arrays obtained through RIFLE Automated Test Equipment of 1Kbit array are reported. Such ATE, ensuring flexibility in terms of signals and timing, allowed evaluating hysteresis and to perform 50k write cycles in a very limited time, getting a first insight on TAS-MRAM arrays performance and reliability.

Erratic bits in Flash Memories under Fowler-Nordheim programming

Since erratic bits have been observed only after erasing in conventional Flash programmed via CHE injection, their nature was related to physical phenomena occurring during erasing [1, 3]. On the other hand, the impulse towards low power Flash applications focuses a new attention over the Fowler-Nordheim (FN) tunneling mechanism for prograrnming and it is important to fully exploit the performances of the standard Flash cell in such conditions. The purpose of this work is to show the existence of erratic bits (hereafter denoted as PE) also after FN programming in standard cells, where electrons are injected into the floating gate from the channel. This result has a relevant impact on the study of the physical nature of erratic bits, since some possible causes can now be ruled out. A full set of statistics about the PE generation and a comparison with erratic bits during erasing (denoted as EE) will be presented.

Threshold voltage spread in flash memories under a constant ΔQ erasing scheme

This paper presents a new erasing scheme for Flash memories characterized by a constant charge injected by each pulse. An analytical expression for the erased threshold voltage as a function of electrical, technological and physical parameters shows their impact on the erased threshold distribution spread. The dynamics of threshold distributions of entire memory sectors is analyzed and the attention is focused on its independence of the initial threshold voltage and on the creation and evolution of the distribution spread.

An Automated Test Equipment for Characterization of Emerging MRAM and RRAM Arrays

In this paper it is presented a test equipment for the characterization of two different emerging memory technologies like the Thermally Assisted Switching-Magnetic Random Access Memory (TAS-MRAM) and the Resistive Random Access Memory (RRAM). The instrument is developed to allow a fast characterization of test array structures and can be potentially adapted for any other non-volatile memory generation. The hardware architecture is based on a PCI S5933 chipset being the local bus interface of a x86-PC that communicates with the units of the system like 14 bits/100 MHz arbitrary waveform generators and 12 bits/70 MHz programmable measurement units. A user-friendly software interface developed in LabVIEW has been implemented to allow large flexibility in changing the test parameters and a fast analysis of the test results. The instrument performance has been evaluated performing the typical non-volatile memory tests such as endurance and disturbs characterizations, running test flows up to 320 hours for MRAM devices and up to 6,137 hours for RRAM devices.