Andrea Donno

A 10-b 50-MSPS Low Power Pipeline ADC for Ultra-High Energy Cosmic Rays Detection

The upgrade of the Pierre Auger Observatory required a larger number of detectors that implies a dramatic increase of the power consumption. As the analog-to-digital converter (ADC) is the most critical circuit block, an integrated solution is here proposed. A 10 b 50-MSps 5-stage pipeline ADC is implemented in 65 nm digital CMOS. It achieves 50.3 dB signal-to-noise and distortion ratio (SNDR), 52.3 dB signal-to-noise ratio (SNR), 59.2 dB spurious free dynamic range (SFDR) for a full-scale input sinewave at Nyquist frequency. The ADC features 12 mW power consumption from a 1.2 V supply, while occupying 0.8 mm2 die area.

A Low-Power Analog Baseband Section for 60-GHz Receivers in 90-nm CMOS

A low-power analog baseband section suitable for 60-GHz receivers using orthogonal frequency-division multiplexing (OFDM) with 16 quadrature amplitude modulation (16-QAM) modulation is presented in this paper. Power efficiency is achieved by combining active-RC with source-follower-based topologies in order to synthesize a custom sixth-order transfer function. The complete chain consists of the cascade of a first-order transimpedance amplifier with finely programmable gain, a fourth-order source-follower-based filter, and a coarse gain first-order programmable gain amplifier. The prototype is implemented in 90-nm CMOS. It achieves a 1-GHz cutoff frequency and programmable gain from 0 to 20 dB with 1-dB step control, drawing 9.5 mA (0-9 dB gain range) or 10.8 mA (10-20 dB gain range) from a 1-V supply. An 8.2-dBm third-order input intercept point and a -145-dBm/Hz input-referred noise power density are measured at 0- and 20-dB gain, respectively. The entire circuit occupies an area of 400 × 390 μm2.

A 9.5mW analog baseband RX section for 60GHz communications in 90nm CMOS

The analog baseband section of a receiver for high data-rate 60GHz wireless communications is implemented in 90nm CMOS. It consists of the cascade of a 1^st-order transimpedance amplifier with finely programmable gain, a 4^th-order source-follower based filter and a coarse gain 1^st-order programmable gain amplifier, resulting in an overall 6^th-order selectivity and a 1GHz cut-off frequency. Gain can be programmed from 0dB up to 20dB with 1dB step control, drawing 9.5mA (0–9dB gain range) or 10.8mA (10–20dB gain range) from a 1V supply. A 8.2dBm IIP3 and a −145dBm/Hz IRN are measured respectively at 0dB and 20dB gain. The entire baseband section occupies 400×390µm² die area.

A 150MHz 3rd-order single Opamp continuous-time analog filter in 28nm CMOS technology

An improved Active-Gm-RC filter architecture is proposed in this paper. With respect to the biquad Active-Gm-RC cell, this architecture exploits the second pole of the Opamp to increase the filter order up to 3, while maintaining single Opamp topology. This reduces the required power per pole. A prototype of the low-pass filter has been designed in 28nm CMOS technology. The filter power consumption is 340μW with a 0.9V voltage supply, cut-off frequency is 150MHz achieving a Figure-of-Merit of 165dB.

A 23mW 4.5/8 GHz IR-UWB transmitter in 65nm TSMC CMOS technology

This paper presents a low power transmitter for Impulse-Radio Ultra-Wideband (IR-UWB) applications. It generate short duration bi-phase modulated UWB pulses with a center frequency of 4.5 / 8 GHz according to the selected channel. A simplified transmitter architecture enabling low power consumption has been adopted. The key circuit is a phase shifter used to obtain positive and negative pulses. Generated pulses comply with requirements of the IEEE 802.15.4a standard. The transmitter is designed in 65nm CMOS technology. Simulations results show that the transmitter consumes 23 mW peak power from a 1.2V supply at 8 GHz of work frequency.

A 0.9V 3rd-order single-OPAMP analog filter in 28nm CMOS-bulk

A 3rd-order 132MHz cut-off frequency low-pass filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μ\ν without that the Signal-to-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-the-art.

A 10-b 100-MSPS low power pipeline ADC for high energy physics experiments

A 10b 100-MS/s five-stage pipeline analog-to-digital converter (ADC) is implemented in 65nm digital CMOS process with power-reduction techniques for high energy physics experiments. It achieves 6.9dB signal-to-noise and distorsion ratio (SNDR). 8.5dB signal-to-noise ratio (SNR), 9.2 effective number of bits (ENOB) for a full-scale input sine at nyquist frequency. The ADC power consumption is 12.7mW from a 1.2V supply. It occupies 0.8mm2 die area.