Marcello De Matteis

A 33 MHz 70 dB-SNR Super-Source-Follower-Based Low-Pass Analog Filter

In this paper, a 4th-order low-pass continuous-time analog filter is presented, that is implemented with the cascade of two efficient and compact biquadratic cells, realized using the Super-Source-Follower topology. The biquadratic cell uses only two capacitors and four transistors: two transistors for the signal processing and two transistors as current sources for biasing purpose. The 4th-order filter prototype has been integrated in 0.18 μm CMOS technology. For a 33 MHz cut-off frequency, the filter performs 18 dBm-IIP3 for two tones at 2 MHz and 3 MHz, with total current of 770 μA from a single 1.8 V supply voltage.

A 7.65-mW 5-bit 90-nm 1-Gs/s Folded Interpolated ADC Without Calibration

Power consumption of high-speed low-resolution analog-to-digital converters (ADCs) can be reduced by means of calibration. However, this solution has some drawbacks such as time slot allocation for calibration and die area increase. This paper presents a 5-bit 1-Gs/s ADC without calibration, fabricated in 90-nm CMOS. Low power consumption has been ensured by operating at both architecture and comparator levels. A folded interpolated architecture has been adopted. However, compared to standard solutions that use static preamplifiers, the interpolation technique has been implemented by taking recourse to dynamic comparators, enabling significant power saving. Moreover, despite the high operating frequency, intrinsic matching has been ensured while keeping low power consumption. The ADC uses double-tail dynamic comparators, operating with a fixed bias current and with reduced kickback noise. Large input transistors are used to guarantee the targeted matching, thereby avoiding calibration. The ADC achieves 4.3b-ENOB (effective number of bits) and 260-MHz effective resolution bandwidth while consuming 7.65 mW from a 1.2 V supply. The ADC figure of meritis 0.39 pJ/conv. step, which is the state-of-the-art performance for an uncalibrated ADC at this sampling frequency and resolution.

Advances on Analog Filters for Telecommunications

The wireless networks popularity rapidly requires a significant effort on low-power low-cost, and highly integrated RF ICs, where the power consumption reduction of the transceiver and of each block becomes of fundamental importance. Analog base-band continuous-time filters embedded in the receiver path are here addressed with three examples. The first example is an active-Gm7-RC filter which uses the opamp frequency response to synthesize the filter behaviour. The second example is a source-follower-based filter cell. A large linearity is achieved for a low overdrive. This with the possibility of realizing a full biquadratic cell in a single branch, requires a low power consumption. Both these examples are suited for UMTS & WLAN receivers. The last example is the gm-gm-C approach which features low-power wide-band CMOS continuous-time low-pass filters with medium resolution, as it is the case of a UWB base-band filter

A dual-band balun LNA resilient to 5–6 GHz WLAN blockers for IR-UWB in 65nm CMOS

In this paper a dual band balun low-noise-amplifier (LNA) for impulse-radio ultra wide band (IR-UWB) applications is proposed. It exploits a common-gate (CG) stage in parallel to a common-source (CS) featuring 18 dB maximum gain, <;4 dB noise figure and 4 dBm in-band third-order intermodulation intercept (IIP3). A double-peak single notch input network with a dual-band LC load is used for input matching and for WLAN (5-6 GHz) out-of-band interferers suppression, resulting in 16 out-of-band IIP3. This allows to remove the 5-6GHz WLAN dedicated filtering at the antenna reducing costs. The dual-band balun-LNA has been designed in 65nm CMOS technology, 1.2V supply and 9mA current consumption.

A 6.4mW, 4.9nV/√Hz, 24dBm IIP3 VGA for a multi-standard (WLAN, UMTS, GSM, and Bluetooth) receiver

A low-power high-linearity variable-gain-amplifier, VGA, in a 0.13 mum CMOS technology to be embedded in a multi-standard receiver (WLAN, UMTS, GSM, and Bluetooth) is reported. This multi-standard receiver architecture presents considerable different VGA requirements (in terms of bandwidth, DC-gain, and common mode input voltage) for the four telecom standards to be processed. Thus the proposed VGA, in addition to the power control, is demanded to accommodate the different standards requirements and feed the one channel filter. The prototype VGA features gain levels from -10dB to 36dB, with a 25dBm IIP3 and an input-referred noise voltage lower than 5nV/radicHz at 0dB DC-gain. This gives a 85dB-DR for the WLAN case. The VGA draws 6.4mA from a single 2.5V supply

A 12dBm IIP3 reconfigurable mixer for high/low band IR-UWB receivers

This paper presents a highly linear low power fully differential downconversion mixer for impulse radio ultra wideband (IR-UWB) receivers. The downconversion mixer is designed for IR-UWB IEEE 802.15.4a standard compliant receivers. It can be reconfigured according to the selected operation channel. In fact, it enables the downconversion of the #3 mandatory channel in low band (4.4928 GHz carrier frequency, 499.2 MHz channel bandwidth), or #9 mandatory channel in high band (7.9872 GHz carrier frequency, 499.2 MHz channel bandwidth), or #11 optional channel in high band (same carrier frequency of channel #9 but 1.331 GHz channel bandwidth). Linearity of the proposed mixer is improved utilizing derivative superposition method and source degenerations at the input stage. The proposed mixer has been designed in a 65 nm CMOS technology. Post layout simulations result in 12 dBm IIP3, 16.8 dB minimum noise figure while consuming 2.7 mW from 1.2 V supply voltage.

A 65nm CMOS technology radiation-hard bandgap reference circuit

This paper presents a BandGap reference circuit with low sensitivity to temperature and to the voltage supply variations. It has been designed to be Radiation-Hard up to 1 GRad. This voltage reference has been developed in a commercial 65nm CMOS technology with 1.2 V of nominal voltage supply. A current-mode architecture has been chosen to allow the low-voltage operation. Particular attention has been dedicated to circuit radiation hardness, in order to provide a stable voltage signal also with high radiation levels, like that of high-energy physics experiments. One of the advantages of CMOS scalingdown process is that the effects, due to radiation exposure, steadily decrease making circuits more and more robust. It follows that, in a conventional BandGap circuit, the most critical aspect could regard the diodes, or in general, the sensing elements. This design has been preceded by a series of measurements of two different sensing device in order to use that with the better radiation hardness .The BandGap reference circuit has been simulated with temperature range from -10 °C to 50 °C. The output value is around 330 mV with a curvature error of 0.05% in nominal conditions. The maximum output deviation in the absolute value is about ±1.1% and ±1.6% under process and mismatch respectively. The integrated noise from 0.01 Hz to 100 MHz is about 180 μV and the power consumption is 240μW. The radiation effects have been simulated modifying the models of devices according to measurements. In this case, thanks to a proper sizing, the output voltage shift is of a few millivolts.

A 65 nm Rad-Hard Bandgap Voltage Reference for LHC Environment

A radiation-hard BGR (bandgap voltage reference) circuit is here presented. Its able to maintain the output voltage accuracy over process, voltage, and temperature (PVT) variations, combined with extremely high total-ionizing-dose (up to 800 Mrad (SiO2)), as required by the next experiments upgrades of the Large Hadron Collider (LHC). The design has been dealt starting from several experimental results, collected from some testing devices, under radiation exposure. In particular, this information has been used modifying the model files provided by foundry, in order to consider the radiation exposure effects during the design process. Consequently, a rad-hard optimized sizing device has been devised. In addition, a particular layout solution has guaranteed a better radiation immunity for the temperature sensing elements (i.e., diodes). The bandgap reference circuit has been fabricated in a commercial 65 nm CMOS technology. Measurement results show a temperature coefficient of about 130 ppm/°C over a temperature range of 120 °C (from -40 °C to 80 °C, as required by application) and a variation of 0.3% for Vdd 1.08 V-1.32 V. The mean value of the BGR output is about 330 mV, with a 10% maximum shift when exposed up to 800 Mrad (SiO2). The power consumption is 240 μW at room temperature, with a core area of 0.018 mm2.

A 28.8-MHz 23-dBm-IIP3 3.2-mW Sallen-Key Fourth-Order Filter With Out-of-Band Zeros Cancellation

In this brief, a 28.8-MHz -3-dB frequency low-pass analog filter is presented. The filter synthesizes a fourth-order Butterworth transfer function, exploiting the well-known Sallen-Key (SK) biquadratic cell. The out-of-band zeros typically present in SK implementations are hereby completely canceled by using a low-power auxiliary path. This leads to a significant improvement of the stop-band rejection, at the cost of a small power for the same auxiliary path biasing. The design exhibits very large in-band IIP3 over the entire filter bandwidth (20 dBm at 10 MHz and 11 MHz), at 3.2-mW power consumption. The filter prototype has been designed in CMOS 0.18-μm technological node. The total area occupancy is 0.12 mm2 and the in-band integrated noise is 101 μVRMS.

A 150MHz 3rd-order single Opamp continuous-time analog filter in 28nm CMOS technology

An improved Active-Gm-RC filter architecture is proposed in this paper. With respect to the biquad Active-Gm-RC cell, this architecture exploits the second pole of the Opamp to increase the filter order up to 3, while maintaining single Opamp topology. This reduces the required power per pole. A prototype of the low-pass filter has been designed in 28nm CMOS technology. The filter power consumption is 340μW with a 0.9V voltage supply, cut-off frequency is 150MHz achieving a Figure-of-Merit of 165dB.