Vincenzo Chironi

A Digitally Modulated Class-E Polar Amplifier in 90 nm CMOS

In this paper a digital amplitude modulator for a polar transmitter is presented. The instantaneous output power is modulated by adjusting the amplifiers load through a digitally controlled impedance transformation network. The modulator is suited for modulation schemes with moderate peak-to-average power ratio (PAPR), such as π/4 DQPSK. The modulator may also be used for fine gain control in constant envelope modulation schemes. A class E amplifier with digital impedance amplitude modulation is integrated in 90 nm CMOS. It achieves a peak output power of 9 dBm with a PAE of 30% when powered from a 1.2 V supply. The measured EVM is 2.6% for a 6 dBm π/4 DQPSK modulated signal with 2 Mb/s signal rate at 2.4 GHz RF frequency.

A dual-band balun LNA resilient to 5–6 GHz WLAN blockers for IR-UWB in 65nm CMOS

In this paper a dual band balun low-noise-amplifier (LNA) for impulse-radio ultra wide band (IR-UWB) applications is proposed. It exploits a common-gate (CG) stage in parallel to a common-source (CS) featuring 18 dB maximum gain, <;4 dB noise figure and 4 dBm in-band third-order intermodulation intercept (IIP3). A double-peak single notch input network with a dual-band LC load is used for input matching and for WLAN (5-6 GHz) out-of-band interferers suppression, resulting in 16 out-of-band IIP3. This allows to remove the 5-6GHz WLAN dedicated filtering at the antenna reducing costs. The dual-band balun-LNA has been designed in 65nm CMOS technology, 1.2V supply and 9mA current consumption.

A Low-Power Analog Baseband Section for 60-GHz Receivers in 90-nm CMOS

A low-power analog baseband section suitable for 60-GHz receivers using orthogonal frequency-division multiplexing (OFDM) with 16 quadrature amplitude modulation (16-QAM) modulation is presented in this paper. Power efficiency is achieved by combining active-RC with source-follower-based topologies in order to synthesize a custom sixth-order transfer function. The complete chain consists of the cascade of a first-order transimpedance amplifier with finely programmable gain, a fourth-order source-follower-based filter, and a coarse gain first-order programmable gain amplifier. The prototype is implemented in 90-nm CMOS. It achieves a 1-GHz cutoff frequency and programmable gain from 0 to 20 dB with 1-dB step control, drawing 9.5 mA (0-9 dB gain range) or 10.8 mA (10-20 dB gain range) from a 1-V supply. An 8.2-dBm third-order input intercept point and a -145-dBm/Hz input-referred noise power density are measured at 0- and 20-dB gain, respectively. The entire circuit occupies an area of 400 × 390 μm2.

An area efficient digital amplitude modulator in 90nm CMOS

This paper presents a digital amplitude modulator (DAM) for polar transmitter in 90 nm CMOS technology. It consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. It reaches an output power of −2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving −26.1 dB error vector magnitudes (EVM) and 18% drain efficiency. The 8-bit are segmented addressed. This results in a very compact 0.007 mm2 chip area.

A 12dBm IIP3 reconfigurable mixer for high/low band IR-UWB receivers

This paper presents a highly linear low power fully differential downconversion mixer for impulse radio ultra wideband (IR-UWB) receivers. The downconversion mixer is designed for IR-UWB IEEE 802.15.4a standard compliant receivers. It can be reconfigured according to the selected operation channel. In fact, it enables the downconversion of the #3 mandatory channel in low band (4.4928 GHz carrier frequency, 499.2 MHz channel bandwidth), or #9 mandatory channel in high band (7.9872 GHz carrier frequency, 499.2 MHz channel bandwidth), or #11 optional channel in high band (same carrier frequency of channel #9 but 1.331 GHz channel bandwidth). Linearity of the proposed mixer is improved utilizing derivative superposition method and source degenerations at the input stage. The proposed mixer has been designed in a 65 nm CMOS technology. Post layout simulations result in 12 dBm IIP3, 16.8 dB minimum noise figure while consuming 2.7 mW from 1.2 V supply voltage.

A 32-channel 12-bits single slope A-to-D converter for LHC environment

The A-to-D converter here presented is part of a bigger system able to sense and monitor electrical/physical parameters in particles detectors, for LHC experiments. The CMOS integrated circuits operating in high-energy environments experience large leakage current and voltage/temperature variations. For this reason in LHC experiments, a proper sensing and monitoring system has been designed with the aim to provide real time information about the electrical/physical scenario for the detectors in LHC. The A-to-D converter has a resolution of 12 bits, is based on single slope architecture and is able to manage 32 input analog channels. The design is challenging for several reasons, considering the required conversion accuracy and the critical physical scenario. The entire A-to-D converter has been fully characterized with process-voltage-temperature variations, obtaining a definitive 11bit accuracy in the worst-case simulation corner. The A-to-D has been designed in CMOS 0.13μm technology, consumes 350μW (including dynamic power due to the digital circuits) and operates at 20MHz clock frequency, for a definitive 2.3kHz sample rate.

A compact digital amplitude modulator in 90nm CMOS

This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of −2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving −26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete−time to continuous−time conversion a 2−fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm2 chip area.

A −19dBm sensitivity integrated RF-DC converter with regulated output voltage for powering UHF wireless sensors

This paper presents a -19dBm sensitivity RF-DC converter for energy harvesting applications. It is able to harvest the energy from a dipole antenna operating at 866.5MHz (European UHF RFID frequency) providing a regulated output voltage in the range between 1.9V to 2.4V over a 2MΩ resistive load. Such voltage level is suitable to supply body sensor nodes. The four stages Dicksons RF-DC rectifier converts the UHF RF input signal to a 2V DC output, feeding the following two stages DC-DC Pelliconis charge pump. The DC-DC charge pump, powered by a 90kHz ring oscillator, is used to further step-up the RF-DC rectifier output voltage and to realize the RF to load isolation. The output voltage regulation is performed by a feedback network made by a hysteresis comparator and a Vt-based voltage reference. The RF-DC converter shows a 38% power conversion efficiency at 0dbm input power level.

A SAW-less dual-band RF front-end for IR-UWB receiver in 65nm CMOS

In this paper a highly linear-dual band RF front-end (LNA and Mixer) for IR-UWB (IEEE 802.15.4a) applications is proposed. LNA exploits a common-gate (CG) stage in parallel to a common-source (CS). It performs single-ended to differential-ended operation, avoiding balun stage. It features 18 dB maximum gain, <;4 dB noise figure and +4 dBm inband third-order intermodulation intercept (IIP3). A double-peak single notch input network with a dual-band LC load is used for input matching and for WLAN (5-6 GHz) out-of-band interferers suppression resulting in +16 dBm out-of-band IIP3. This allows to remove the 5-6GHz WLAN dedicated filtering at the antenna reducing costs. The proposed mixer is a Gilbert cell and features derivative superposition method and source degenerations at the input stage to improve linearity performance showing > +11.8 dBm IIP3. The RF front-end receiver has been designed in 65nm CMOS technology consuming 13.5 mW.

A 5.8–13 GHz SDR RF front-end for wireless sensors network robust to out-of-band interferers in 65nm CMOS

In this paper a highly-linear software defined radio front-end (LNA and Mixer) for wireless sensor networks in the 5.8-to-13 GHz frequency range is presented. It is suitable to IEEE 802.15.4a and IEEE 802.15.4a and upcoming different standards. The RF front-end features a very high robustness to out-of-band interference (OBI) thanks to mixer-based RF blocker filtering. This allows to remove any dedicated filtering at the antenna reducing costs. The low noise amplifier exploits a common-gate (CG) stage in parallel to a common-source (CS) performing the single-ended to differential-ended conversion avoiding off-chip balun stage. The analog front-end provides 21.6-25.6 dB conversion gain, 2.16-4 dB noise figure and 2.6-5.1 dBm in-band IIP3 over 5.8 GHz to 13 GHz. It tolerates -5 dBm blockers at 100 MHz offset for input-referred 1-dB desensitization. This work has been designed in 65nm CMOS technology, 1.2V supply and 9 mA current consumption.