Andrea Pacelli

Self-consistent 2-D model for quantum effects in n-MOS transistors

We present a self-consistent two-dimensional (2-D) model for carrier quantization effects in the channel of highly-doped n-MOSFETs. Quantization is taken into account inside a box region surrounding the inversion channel. The proposed approach extends previously proposed one-dimensional (1-D) schemes allowing one to estimate the quantum mechanical (QM) effects on the device current. Good convergence properties are achieved exploiting the effective intrinsic density concept. The simulator has been applied to MOS devices with different peak channel doping, resulting in an improved description of the device behavior.

Compact modeling of thermal resistance in bipolar transistors on bulk and SOI substrates

Analytical expressions for the thermal resistance of bipolar transistors on bulk and SOI substrates are presented. The models are derived on the basis of intuitive physical pictures and validated by comparison with experimental data and three-dimensional (3D) device simulation. The effect of bulk and SOI substrates, shallow- and deep-trench isolation, and multiple emitter fingers is accounted for. All models are suitable for both hand calculations and computer-aided design.

Polysilicon quantization effects on the electrical properties of MOS transistors

The quantum-mechanical behavior of charge carriers at the polysilicon/oxide interface is investigated. It is shown that a dark space depleted of free carriers is created at the interface as a consequence of the abrupt potential energy barrier, which dominates the polysilicon capacitance and voltage drop in all regions of operation of modern MOS devices. Quantum-mechanical effects in polysilicon lead to a reduction in the gate capacitance in the same way as substrate quantization, and to a negative voltage shift, which is opposed to the positive shift caused by carrier quantization in the channel. Effects on the extraction of device physical parameters such as oxide thickness and polysilicon doping are also addressed.

A local circuit topology for inductive parasitics

A novel circuit topology for inductive coupling between interconnecting wires is presented. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for long-range coupling by propagating the vector potential from one wire to the next. Examples of model calibration, both directly from layout and as model-order reduction of a given inductance matrix, are presented for simple wiring structures.

Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI

We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region underneath results in a very low collector-to-substrate capacitance. We also show that this process option achieves a much lower thermal resistance than using SOI with deep trench isolation, both reducing cost and curbing self-heating effects.

Generation of equivalent circuits from physics-based device simulation

A novel technique for the numerical extraction of equivalent circuits from physics-based device simulation is presented. The method is based on the partitioning of the device into functional regions, each corresponding to a circuit block. All the circuit elements have a clear physical interpretation. Element values are directly obtained from small-signal dc device simulation. The method generates equivalent circuits of a complexity similar to the traditional approach, with model generation times comparable with those of black-box and physics-based device models. Applications to one-dimensional pn junctions and bipolar transistors are presented, discussing the extraction algorithm in detail.

A drift-diffusion/Monte Carlo simulation methodology for Si/sub 1-x/Ge/sub x/ HBT design

An accurate and efficient simulation methodology for Si/sub 1-x/Ge/sub x/ HBTs is presented. A two-dimensional (2-D) drift-diffusion solver is employed for dc and ac characteristics, and one-dimensional (1-D) full-band Monte Carlo for transport in the base-collector high-electric-field region. Extrinsic parasitics are introduced as lumped circuit elements whose values are obtained from measurements and layout considerations. This approach not only reduces the computational cost of the simulation, but it also helps to differentiate the relevance of the intrinsic and extrinsic device parameters. We discuss the calibration of the simulation on a 0.25 /spl mu/m process and use a 1-D regional analysis in the quasi-static approximation to identify the major source of delay. Results of the delay analysis were used to improve device performance for the 0.16 /spl mu/m technology node.

An improved formula for the determination of the polysilicon doping

This letter describes an improved formula for the extraction of the polysilicon doping from the C-V characteristic of MOS transistors. Analytical approximations are presented for the inversion layer contribution, which was neglected in previous work. The new approach returns an estimate error smaller than 10% when the full substrate and poly quantization are accounted for. Practical application to experimental data is also addressed.

Simulation of polysilicon quantization and its effect on n- and p-MOSFET performance

Abstract In this work we investigate the effect of quantization at the polysilicon/oxide interface on the properties of n- and p-MOS transistors. As a consequence of the potential energy barrier, a dark space depleted of free carriers is created at the interface, which is slightly dependent on the applied bias. Both polysilicon capacitance and voltage drop in all regions of operation of modern MOS devices are dominated by quantum effects. Polysilicon quantization leads to a reduction in the gate capacitance in the same way as substrate quantization, and to a negative voltage shift, which is opposed to conventional substrate quantization. These effects are discussed in detail for dual-gate MOSFETs with ultra-thin oxides.

Monte Carlo simulation of impact ionization in SiGe HBTs

Measurements and Monte Carlo simulations of impact ionization in the base-collector region of SiGe HBTs are presented. A device with low germanium concentration (graded from 0 to 12%) is considered and no differences are found between the experimental multiplication factor in that device and the corresponding silicon control. Because impact ionization (II) occurs inside the bulk-Si collector, phonon and II scattering rates for bulk silicon can be used in the Monte Carlo simulation, avoiding the need to model the strained SiGe layers. Full-Band Monte Carlo simulations are shown to reproduce the multiplication factors measured in SiGe devices featuring different collector profiles.