Andrew Adams

A 10/20/30/40 MHz Feedforward FIR DAC Continuous-Time

The first feedforward continuous-time ΔΣ ADC with a finite impulse response (FIR) DAC is presented for consumer radio applications. It provides robust loop-delay compensation with no performance degradation in the presence of radio out-of-band blockers from either out-of-band gain peaking in the signal transfer function or blocker clock-jitter modulation. A half-clock-period-delay half-return-to-open FIR DAC minimizes intersymbol interference with 3 dB less noise. At 20/30/40 MHz operation, the figure-of-merit (FOM) is less than or equal to 36 fJ/conv.-step. At 10 MHz operation, the FOM is 50 fJ/conv.-step. The equivalent FOM for a 20 MHz-only design is 28 fJ/conv.-step. It occupies 0.0194 mm2 in 40 nm CMOS and is the smallest wideband ADC ever reported.

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Sine-wave synthesizers are a core requirement in many electronic applications, such as communication systems, and test and verification of analog/mixed-signal electronic systems. In sine-wave synthesizers, there exists a compromise between output spectral purity and hardware complexity. Harmonic-cancelling sine-wave synthesizers (HCSSs) allow spectrally pure signal synthesis at low hardware cost, compared to conventional sine-wave synthesis approaches. In this paper, we propose a digital HCSS hardware architecture, which is simpler, more hardware efficient and more programmable compared to state of the art HCSSs. The proposed architecture has been verified through a prototype built from an FPGA and discrete components. Prototype results demonstrate 51.9 dBc spurious free dynamic range (SFDR) and an output frequency range from 100 Hz to 100 kHz.

ADC With Robust Blocker Performance for Radio Receivers

Digital harmonic-cancelling sine-wave synthesizers (DHSSs) use a 47 year old concept, recently revived as a power and area efficient solution for on-chip sine-wave synthesis. The operation of a DHSS involves amplitude scaling and summing a set of square-waves to produce a sampled sine-wave. The circuit which performs the scaling and summing operation is referred to as the harmonic-cancelling digital-to-analog converter (HC-DAC). Unlike a regular DAC whose amplitude weights are defined by powers of two, an HC-DAC’s amplitude weights are defined by a sine function. Thus, HC-DACs present intriguing design problems which cannot be solved using the conventional knowledge gathered from designing regular DACs. One such problem is managing the effect of mismatch between unit-elements in HC-DACs. This paper proposes a partial dynamic element matching (DEM) technique tailored for HC-DACs, which reduces the effect of mismatch, while preserving the power and area efficiency of DHSSs. The effectiveness of the DEM technique is evaluated using a DHSS circuit fabricated in an STMicroelectronics 130 nm CMOS technology. Test results show that applying the DEM technique increased the figure-of-merit of the DHSS by 40% at 2 MHz output frequency.

A simple digital architecture for a harmonic-cancelling sine-wave synthesizer

The first (single-bit) feed-forward (FF) FIR DAC continuous-time (CT)-ΔΣ ADC is presented for cellular radio applications. It provides a robust loop delay compensation with no performance degradation in the presence of radio out-of-band blockers; a known drawback of FF CT-ΔΣ ADCs. At 20/30/40 MHz operation, the FOM is less than or equal to 36 fJ/conv. At 10 MHz operation, the FOM is 50 fJ/conv. The equivalent FOM for a 20-MHz-only design is 28 fJ/conv. It occupies 0.0194 mm2 in 40 nm CMOS.

Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis

Digitization from IF or RF using an LC bandpass ΔΣ modulator avoids the traditional problems of direct-conversion receivers, such as EVM degradation due to IQ imbalance, 2nd-order intermodulation, and AGC interaction with DC offset correction settling. Our target application is a low-power IEEE 802.11n receiver for 2.4 to 2.5GHz using a fixed 3.2GHz clock and IF tuned from 700 to 800MHz. The fixed clock allows an integer-N PLL with high reference frequency (40MHz, for example), which allows wide loop bandwidth and low phase noise, even at mW-level power consumption (e.g. [1]). The power savings from simplified LO generation are also important. Sampling from IF with an fs/4 modulator rather than sampling from RF with a 3fs/4 modulator (as in [2]) gives higher ADC SNR because Q-enhanced LC filters have a tradeoff between Q and SNR and the loop filter fractional bandwidth is greater at the lower center frequency.

A 10/20/30/40 MHz feed-forward FIR DAC continuous-time ΔΣ ADC with robust blocker performance for radio receivers

An on-chip sine-wave synthesizer design with fast programmability and low hardware cost is presented. The design makes use of a harmonic cancellation technique to digitally synthesize an approximation to a sine-wave, which does not contain lower order harmonic distortions. The remaining higher order harmonics are attenuated with the use of a low pass filter (LPF) to synthesize a spectrally pure sine-wave. The simple nature of the sine-wave synthesis approach allows for a design with low hardware cost while maintaining high output spectral purity. The generic design of the aptly named digital harmonic-cancelling sine-wave synthesizer (DHSS) is discussed along with parasitic extracted simulation results from a prototype designed in a 0.13 μm CMOS process. Simulation results demonstrate that the DHSS prototype is capable of synthesizing up to 100 MHz output frequency, with 43.5 dB SFDR, while consuming only 2.26 mW of power.

An LC bandpass ΔΣ ADC with 70dB SNDR over 20MHz bandwidth using CMOS DACs

Digital harmonic-cancelling sine-wave synthesizers (DHSSs) enable programmable, low cost, spectrally pure, sinusoidal signal synthesis for application areas such as communication systems, and on-chip testing of analog/mixed-signal integrated circuits. The implementation of a DHSS requires a digital-to-analog converter (DAC). However, unlike a conventional binary-coded DAC, the harmonic-cancelling DAC (HC-DAC) used in a DHSS scales the input digital signals by a set of irrational amplitude weights. Consequently, the conventional knowledge of how amplitude resolution affects a binary-coded DAC does not apply to HC-DACs. In this paper, we present a mathematical study of how amplitude resolution and unit-element mismatch affects the signal-todistortion (SDR) ratio of an HC-DAC. The results of the study show that it is possible to find a Pareto optimal value of amplitude resolution for a given HC-DAC with a target SDR. The values of SDR estimated from the mathematical model have been verified against circuit simulation results from two HC-DAC designs created using a 013 μm CMOS technology.

Design of a digital harmonic-cancelling sine-wave synthesizer with 100 MHz output frequency, 43.5 dB SFDR, and 2.26 mW power

In [1] , Table I compares the state of the art in CT

The effect of amplitude resolution and mismatch on a digital-to-analog converter used for digital harmonic-cancelling sine-wave synthesis

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Corrections to “A 10/20/30/40 MHz Feed-Forward FIR DAC Continuous-Time

ADCs. Unfortunately, due to a mistake, the FOM [Schreier] (dB) reported is 3 dB below its actual value. Table I in [1] is reprinted as Table I . The authors regret their mistake.