Andrew Pan

A Quasi-Analytical Model for Double-Gate Tunneling Field-Effect Transistors

Tunneling field-effect transistors (TFETs) are being widely investigated as a post-CMOS technology; however, despite significant experimental efforts, no quantitatively accurate device models are available. We derive an expression which provides the complete current characteristics of the double-gate TFET and demonstrate its agreement with simulation. This model will be useful in the design and circuit analysis of TFETs.

Electrostatic Modeling and Insights Regarding Multigate Lateral Tunneling Transistors

We use pseudo-2-D analytical models to study the electrostatics of multigate tunneling field-effect transistors (TFETs), providing a portable set of equations to simultaneously describe silicon-on-insulator, double gate, and cylindrical nanowire devices. We validate the model via extensive comparisons with numerical simulations and demonstrate its accuracy and general applicability; 2-D tunneling effects are analytically estimated and found to be small for well-scaled devices within the semiclassical model. We also study the impact of source and drain doping on TFET performance, including a seminal analytical treatment of nonabrupt junctions and degeneracy effects. We present a new simple model to explain the adverse effects of excessive source doping, and show for the first time how degeneracy in low density-of-states materials directly degrades not only the tunneling efficiency, but also the device electrostatics, causing particular problems for III-V p-TFETs.

Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless FinFET Technologies

In this paper, we develop an evaluation framework to assess variability in nanoscale inversion-mode (IM) and junctionless (JL) fin field-effect transistors (FinFETs) due to line edge roughness (LER) and random dopant fluctuation (RDF) for both six transistor (6T) static random access memory (SRAM) design and large-scale digital circuits. From a device-level perspective, JL FinFETs are severely impacted by process variations: up to 40% and 60% fluctuation in threshold voltage is observed from LER RDF. Conversely, results show that variability-induced shifts and broadening of timing and power in large-scale digital circuits are not significant and can be accommodated in the design budget. However, we find that LER has a large impact on static noise margin analysis of 6T SRAMs. Required Vccmin values for SRAMs using JL devices reach up to 2× those implemented in conventional IM technologies. The yield for JL SRAM is completely compromised in the presence of realistic levels of LER and RDF. Fortunately, the impact of variability is somewhat reduced with scaling for JL designs; both LER and RDF induce less variation for the 15-nm node compared with the 32-nm node. The observed reduction in Vccmin with technology scaling suggests that digital circuits implemented with JL FinFETs may eventually offer the same level of operability as those based on IM FinFETs, especially in the presence of circuit-level SRAM robustness optimizations.

Channel length dependent sensitivity of Schottky contacted silicon nanowire field-effect transistor sensors

In this paper, we examine the dependence of channel length on the sensitivity of Schottky contacted silicon nanowire field-effect transistor sensors. The fabricated experimental devices are used as photosensors as well as chemical sensors for pH sensing. The difference in light illuminated current response depends on the channel length in the linear regime. However, the current ratio (ΔILight-Dark/IDark) shows a different trend, being much improved for a longer channel in the subthreshold regime, which can be explained by the different subthreshold swings. Finally, devices of two different channel lengths are applied to detect the pH value of a solution yielding results similar to photosensing. From these results, we suggest that it is desirable to shorten the channel if the sensor is working in the linear region and increase the channel length if the sensor is used in the subthreshold region.

PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices

Evaluation of novel devices in the context of circuits is crucial to identifying and maximizing their value. We propose a new framework, Pareto optimization-based circuit-level evaluator for emerging device (PROCEED), that uses comprehensive performance, power, and area metrics for accurate device-circuit coevaluation through optimization of digital circuit benchmarks. The PROCEED assesses technology suitability over a wide operating region (megahertz to gigahertz) by leveraging available circuit knobs (threshold voltage assignment, power management, sizing, and so on). It improves the benchmark accuracy by

Modeling direct interband tunneling. II. Lower-dimensional structures

3\times

PROCEED: A pareto optimization-based circuit-level evaluator for emerging devices

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Junctionless Silicon and In 0.53 Ga 0.47 As Transistors—Part II: Device Variability From Random Dopant Fluctuation

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Gate-Induced Source Tunneling FET (GISTFET)

compared with the existing methods while offering orders of magnitude improvements in runtime over full physical design implementation flows. To illustrate the PROCEEDs capabilities, we deploy it to assess emerging technologies, including novel tunneling field-effect transistors, compared with conventional silicon CMOS. As a further illustration, we extend PROCEED to evaluate future heterogeneous integration of varied devices onto the same silicon substrate.

Modeling direct interband tunneling. I. Bulk semiconductors

We investigate the applicability of the two-band Hamiltonian and the widely used Kane analytical formula to interband tunneling along unconfined directions in nanostructures. Through comparisons with k·p and tight-binding calculations and quantum transport simulations, we find that the primary correction is the change in effective band gap. For both constant fields and realistic tunnel field-effect transistors, dimensionally consistent band gap scaling of the Kane formula allows analytical and numerical device simulations to approximate non-equilibrium Greens function current characteristics without arbitrary fitting. This allows efficient first-order calibration of semiclassical models for interband tunneling in nanodevices.