Shaodi Wang

Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory

Spin-transfer torque random access memory (STT-RAM), as a promising nonvolatile memory technology, faces challenges of high write energy and low density. The recently developed magnetoelectric random access memory (MeRAM) enables the possibility of overcoming these challenges by the use of voltage-controlled magnetic anisotropy (VCMA) effect and achieves high density, fast speed, and low energy simultaneously. As both STT-RAM and MeRAM suffer from the reliability problem of write errors, we implement a fast Landau-Lifshitz-Gilbert equation-based simulator to capture their write error rate (WER) under process and temperature variation. We utilize a multi-write peripheral circuit to minimize WER and design reliable STT-RAM and MeRAM. With the same acceptable WER, MeRAM shows advantages of 83% faster write speed, 67.4% less write energy, 138% faster read speed, and 28.2% less read energy compared with STT-RAM. Benefiting from the VCMA effect, MeRAM also achieves twice the density of STT-RAM with a 32 nm technology node, and this density difference is expected to increase with technology scaling down.

Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless FinFET Technologies

In this paper, we develop an evaluation framework to assess variability in nanoscale inversion-mode (IM) and junctionless (JL) fin field-effect transistors (FinFETs) due to line edge roughness (LER) and random dopant fluctuation (RDF) for both six transistor (6T) static random access memory (SRAM) design and large-scale digital circuits. From a device-level perspective, JL FinFETs are severely impacted by process variations: up to 40% and 60% fluctuation in threshold voltage is observed from LER RDF. Conversely, results show that variability-induced shifts and broadening of timing and power in large-scale digital circuits are not significant and can be accommodated in the design budget. However, we find that LER has a large impact on static noise margin analysis of 6T SRAMs. Required Vccmin values for SRAMs using JL devices reach up to 2× those implemented in conventional IM technologies. The yield for JL SRAM is completely compromised in the presence of realistic levels of LER and RDF. Fortunately, the impact of variability is somewhat reduced with scaling for JL designs; both LER and RDF induce less variation for the 15-nm node compared with the 32-nm node. The observed reduction in Vccmin with technology scaling suggests that digital circuits implemented with JL FinFETs may eventually offer the same level of operability as those based on IM FinFETs, especially in the presence of circuit-level SRAM robustness optimizations.

PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices

Evaluation of novel devices in the context of circuits is crucial to identifying and maximizing their value. We propose a new framework, Pareto optimization-based circuit-level evaluator for emerging device (PROCEED), that uses comprehensive performance, power, and area metrics for accurate device-circuit coevaluation through optimization of digital circuit benchmarks. The PROCEED assesses technology suitability over a wide operating region (megahertz to gigahertz) by leveraging available circuit knobs (threshold voltage assignment, power management, sizing, and so on). It improves the benchmark accuracy by

PROCEED: A pareto optimization-based circuit-level evaluator for emerging devices

3\times

Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operations

to

MTJ variation monitor-assisted adaptive MRAM write

115\times

MEMRES: A Fast Memory System Reliability Simulator

compared with the existing methods while offering orders of magnitude improvements in runtime over full physical design implementation flows. To illustrate the PROCEEDs capabilities, we deploy it to assess emerging technologies, including novel tunneling field-effect transistors, compared with conventional silicon CMOS. As a further illustration, we extend PROCEED to evaluate future heterogeneous integration of varied devices onto the same silicon substrate.

Source Line Sensing in Magneto-Electric Random-Access Memory to Reduce Read Disturbance and Improve Sensing Margin

Evaluation of novel devices in a circuit context is crucial to identifying and maximizing their value. We propose a new framework, PROCEED, and metrics for accurate device-circuit co-evaluation through proper optimization of digital circuit benchmarks. PROCEED assesses technology suitability over a wide operating region (MHz to GHz) by leveraging available circuit knobs (Vt assignment, power management, sizing, etc.) and improves accuracy by 3X to 115X compared to existing methods while offering orders of magnitude improvements in runtime over full physical design implementation flows. To illustrate PROCEEDs capabilities, we deploy it to assess novel tunneling transistors (TFETs) compared to conventional CMOS.

An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits

The adoption of spin-transfer torque random access memory (STT-RAM) into nonvolatile memory systems faces three major obstacles: high write energy, low sensing margin, and high read disturbance. Many designs have been suggested to resolve each of these challenges separately and at the cost of significant overhead. We propose a single low-overhead solution to all these problems without changing the underlying memory architecture by using negative differential resistance devices like tunnel diodes or tunnel field-effect transistors to assist the STT-RAM write and read process. We show through simulations that the proposed designs can dramatically improve the write and read energy efficiency and sensing margins while minimizing the read disturbance, even after accounting for process variations. Our results open a design path for energy-efficient and reliable STT-RAM technologies.

Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing

Spin-transfer torque random access memory (STT-RAM) and magnetoelectric random access memory (MeRAM) are promising non-volatile memory technologies. But STT-RAM and MeRAM both suffer from high write error rate due to thermal fluctuation of magnetization. Temperature and wafer-level process variation significantly exacerbate these problems. In this paper, we propose a design that adaptively selects optimized write pulse for STT-RAM and MeRAM to overcome ambient process and temperature variation. To enable the adaptive write, we design specific MTJ-based variation monitor, which precisely senses process and temperature variation. The monitor is over 10X faster, 5X more energy-efficient, and 20X smaller compared with conventional thermal monitors of similar accuracy. With adaptive write, the write latency of STT-RAM and MeRAM cache are reduced by up to 17% and 59% respectively, and application run time is improved by up to 41%.