Greg Leung

Variability Impact of Random Dopant Fluctuation on Nanoscale Junctionless FinFETs

Junctionless fin held-effect transistor (FinFET) variability due to random dopant fluctuation (RDF) was investigated for sub-32-nm technology generations using technology computer-aided design (TCAD) simulations. Results indicate that variations in threshold voltage, drive current, leakage current, and drain-induced barrier lowering are heavily impacted by RDF for junctionless FinFETs with sufficiently high channel doping (greater than 1019 cm-3). Unexpectedly, the RDF impact is found to be less severe for finer technology generations, although the overall magnitude is still significant compared to line-edge-roughness-induced variability.

Stochastic Variability in Silicon Double-Gate Lateral Tunnel Field-Effect Transistors

Device-level variability in silicon double-gate lateral tunnel field-effect transistors (TFETs) due to line-edge roughness (LER) and random dopant fluctuation (RDF) is investigated for designs with a 20-nm gate length and body widths of 5 or 10 nm (“20/5” and “20/10,” respectively). Variability in TFET threshold voltage (VT), on-state drive current (Ion), off-state leakage current (Ioff), and subthreshold swing is examined by means of statistical technology computer-aided design simulations with consideration of body LER up to 1 nm in amplitude as well as RDF for body heights ranging from 10 to 40 nm. The effects of body LER and RDF are found to be similar in magnitude and also comparable to those in similarly designed fin FETs, with the exception of Ion variability which is roughly three times higher for TFETs. Arguments are presented to explain these findings based on the operating principle of TFETs compared to standard metal-oxide-semiconductor-FET-based technology.

Variability of Inversion-Mode and Junctionless FinFETs due to Line Edge Roughness

We investigated the variability impact of line edge roughness (LER) on standard inversion-mode (IM) and junctionless FinFETs (JL-FinFET) designed for the 2009 ITRS high-performance logic 32-, 21-, and 15-nm nodes using technology computer-aided design simulations. Fluctuations in threshold voltage, drive current, leakage current, subthreshold swing, and drain-induced barrier lowering were found to be significantly worse in junctionless devices compared to IM devices at root-mean-square LER amplitudes up to 1 nm. We invoke a simple physical argument to explain these findings based on the operating principles of IM and junctionless devices and the specific means by which LER affects both device architectures. Our findings show that JL-FinFETs are inherently more sensitive to variability than standard IM devices and will pose significant challenges as a feasible post-CMOS technology.

Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32-nm FinFET Technologies

The variability impact of line edge roughness (LER) on sub-32-nm fin-shaped FET (FinFET) technologies is investigated from both device- and circuit-level perspectives using computer-aided design simulations. Resist-defined FinFETs exhibit sizeable device performance variation (up to 10% fluctuation in threshold voltage and 200% in leakage current) when subjected to fin roughness up to 1 nm root-mean-square amplitude. Spacer-defined FinFETs show negligible device performance variation and exhibit quadratic dependence with LER amplitude. For both patterning technologies, the resulting impact on large-scale digital-circuit performance variation is found to be minimal in terms of the overall delay mean and variation. This is attributed to self-averaging of uncorrelated LER effects between individual devices within the circuits, resulting in minimal delay impact for digital-circuit design. The impact of LER on leakage power variation is also found to be minimal for all technologies; however, the mean value increases by up to 40% for 15-nm resist FinFETs. On this basis, the impact of LER on sub-32-nm FinFET device-level variability is only significant for resist devices, whereas the resulting digital-circuit impact is important only in terms of mean leakage power increase.

Interactions Between Line Edge Roughness and Random Dopant Fluctuation in Nonplanar Field-Effect Transistor Variability

Investigations on device variability for three different emerging field-effect transistor (FET) technologies are performed to determine the statistical dependence or independence of line edge roughness (LER) and random dopant fluctuation (RDF) variability mechanisms. The device candidates include standard inversion-mode (IM) FinFETs, junctionless (JL) FinFETs, and tunnel FETs (TFETs) designed for sub-32-nm generations. Using technology computer-aided design simulations, extracted standard deviations in linear and saturation threshold voltages ( VT,lin and (VT,sat), ON-state current (ION), OFF-state current (IOFF), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) are compared for the cases: 1) when LER and RDF are separately modeled during device simulations and assumed to combine in an uncorrelated fashion, and 2) when LER and RDF are simultaneously modeled in device simulations and no assumption is made about their interaction. After performing the comparisons for each FET technology, we find that LER and RDF cannot be considered independent for IM-FinFETs and TFETs, but can be for JL-FinFETs. The different outcomes are related to local versus distributed variability dependencies in each transistor type. Our conclusions reinforce the need for more comprehensive treatment of variability effects to provide accurate estimations of expected device variability in junction-based FETs.

Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless FinFET Technologies

In this paper, we develop an evaluation framework to assess variability in nanoscale inversion-mode (IM) and junctionless (JL) fin field-effect transistors (FinFETs) due to line edge roughness (LER) and random dopant fluctuation (RDF) for both six transistor (6T) static random access memory (SRAM) design and large-scale digital circuits. From a device-level perspective, JL FinFETs are severely impacted by process variations: up to 40% and 60% fluctuation in threshold voltage is observed from LER RDF. Conversely, results show that variability-induced shifts and broadening of timing and power in large-scale digital circuits are not significant and can be accommodated in the design budget. However, we find that LER has a large impact on static noise margin analysis of 6T SRAMs. Required Vccmin values for SRAMs using JL devices reach up to 2× those implemented in conventional IM technologies. The yield for JL SRAM is completely compromised in the presence of realistic levels of LER and RDF. Fortunately, the impact of variability is somewhat reduced with scaling for JL designs; both LER and RDF induce less variation for the 15-nm node compared with the 32-nm node. The observed reduction in Vccmin with technology scaling suggests that digital circuits implemented with JL FinFETs may eventually offer the same level of operability as those based on IM FinFETs, especially in the presence of circuit-level SRAM robustness optimizations.

Junctionless Silicon and In 0.53 Ga 0.47 As Transistors—Part II: Device Variability From Random Dopant Fluctuation

Random dopant fluctuation (RDF) variability in nanoscale junctionless FETs (JLFETs) utilizing either Si or In0.53Ga0.47As channels has been studied using technology computer-aided design (TCAD) simulations. The 15nm node Si and InGaAs JLFETs are equivalently designed and calibrated using nonequilibrium Greens function simulations for statistical TCAD analysis. We find that n-InGaAs JLFETs exhibit reduced RDF variability compared with n-Si JLFETs in terms of threshold voltage, subthreshold swing, and drain-induced barrier lowering as a result of high degeneracy effects. By contrast, the variability of p-InGaAs JLFETs is comparable with that of n- and p-Si JLFETs because of the larger valence band density of states (DOS). The normalized variations in ON-state drive current are roughly equal (~16%) for all device types, because the major effects of degenerate screening on current transport effectively cancel one another. From these results, we find that high carrier degeneracy in small DOS materials can have a significant effect on the electrostatic integrity of JLFETs in the presence of RDF (especially in subthreshold), and that degenerately doped n-InGaAs devices are slightly (and inherently) more immune to RDF compared with Si JLFETs.

An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits

We develop an evaluation framework to assess the potential benefits of feature-level heterogeneous integration (HGI) in nanoscale VLSI circuits. We study, for the first time, the impact of HGI on circuit delay, layout area, and power by comparing the integration of 15-nm InGaAs and Ge FinFETs via nanotransfer printing with the baseline Si-only FinFET technology. To properly account for the performance, power, and area tradeoffs, we perform comprehensive evaluations, including synthesis, placement, and routing of digital circuit benchmarks. We show the circuits designed with an HGI exhibit lower delay and power due to improved device performance at the cost of larger area induced by misalignment errors. We also demonstrate that the HGI misalignment area penalties can be drastically reduced using posttransfer fin trimming. Our findings provide substantial motivation for industry to explore HGI as a technology route for the post-Si era.

Junctionless Silicon and In 0.53 Ga 0.47 As Transistors—Part I: Nominal Device Evaluation With Quantum Simulations

Despite many experimental demonstrations of III-V junctionless field-effect transistors (JLFETs), few theoretical studies have investigated their performance. We perform nonequilibrium Greens function simulations to compare the merits of silicon and In0.53Ga0.47As JLFETs, including impurity, phonon, and surface roughness (SR) scattering effects through phenomenological self-energies. When ballistic transport is assumed, silicon is superior due to its higher density of states; however, we show that the presence of impurity scattering drastically alters the comparison and leads to significant performance advantages for InGaAs JLFETs. This advantage is lessened but not eliminated by SR effects, which play a more significant role in InGaAs than in silicon based on current experimental parametrizations. We also find that the degradation of electrostatic integrity in III-V devices stemming from higher material permittivity can be mitigated by channel barrier height increases caused by high electron degeneracy. Our results validate InGaAs JLFETs as promising candidates for postsilicon device technologies.

Carbon-ionogel supercapacitors for integrated microelectronics.

To exceed the performance limits of dielectric capacitors in microelectronic circuit applications, we design and demonstrate on-chip coplanar electric double-layer capacitors (EDLCs), or supercapacitors, employing carbon-coated gold electrodes with ionogel electrolyte. The formation of carbon-coated microelectrodes is accomplished by solution processing and results in a ten-fold increase in EDLC capacitance compared to bare gold electrodes without carbon. At frequencies up to 10 Hz, an areal capacitance of 2.1 pF μm(-2) is achieved for coplanar carbon-ionogel EDLCs with 10 μm electrode gaps and 0.14 mm(2) electrode area. Our smallest devices, comprised of 5 μm electrode gaps and 80 μm(2) of active electrode area, reach areal capacitance values of ∼0.3 pF μm(-2) at frequencies up to 1 kHz, even without carbon. To our knowledge, these are the highest reported values to date for on-chip EDLCs with sub-mm(2) areas. A physical EDLC model is developed through the use of computer-aided simulations for design exploration and optimization of coplanar EDLCs. Through modeling and comparison with experimental data, we highlight the importance of reducing the electrode gap and electrolyte resistance to achieve maximum performance from on-chip EDLCs.