Philipp Lindorfer

Substrate Current Independent Hot Carrier Degradation in NLDMOS Devices

Automotive and telecom applications often require voltages in the 20-30V range. These circuits combine high performance CMOS with a high voltage MOS transistor. A possible choice for the high voltage device is an n-channel lateral DMOS transistor (NLDMOS). An advantage of an NLDMOS transistor is that it can be easily integrated within existing technologies without significant process changes. In most cases, though, the drain drift implant must be optimized to meet breakdown voltage and hot carrier reliability requirements. This paper focuses on understanding anomalous hot carrier results obtained from an NLDMOS transistor whose drain drift implant dose was varied

Anomalous Safe Operating Area and Hot Carrier Degradation of NLDMOS Devices

Automotive and telecom applications often require voltages in the 20-30 V range. These circuits combine high-performance CMOS with a high-voltage MOS transistor. A possible choice for the high-voltage device is an n-channel lateral DMOS (NLDMOS) transistor. An advantage of an NLDMOS transistor is that it can be easily integrated within existing technologies without significant process changes. In most cases, though, the drain drift implant must be optimized to meet safe operating area (SOA) and hot carrier (HC) reliability requirements. This paper focuses on understanding anomalous SOA and HC results obtained from an NLDMOS transistor whose drain drift implant dose was varied

Electrical characteristics and reliability of extended drain voltage NMOS devices with multi-RESURF junction

The object of this study is to experimentally validate the usefulness of the multi-RESURF and diluted junction methodology to improve the electrical characteristics of lateral extended drain voltage NMOS. Electrical and hot carrier degradation characteristics are discussed. Significant improvement in the device electrical characteristics is shown, while hot carrier degradation was found to be the limiting factor.

Thermoreflectance CCD Imaging of Self-Heating in Power MOSFET Arrays

Thermoreflectance imaging with high spatial resolution is used to inspect self-heating distribution in active high power (4A) metal-oxide-semiconductor field-effect transistor transistor arrays designed for high-frequency (MHz) operation. Peak temperature change and self-heating distribution is analyzed for both low- and high-dc bias cases and for different ambient die temperatures (296-373 K). Thermoreflectance images reveal temperature nonuniformity greater than a factor of two over the full area of the transistor arrays. Thermal nonuniformity is revealed to be strongly dependent on both bias level and ambient die temperature. Verification based on the fine grain power dissipation in the transistor array was performed using the R3D method for electrical simulation and power blurring for thermal simulation. Results demonstrate thermoreflectance imaging as an effective tool for fast submicrometer noncontact thermal characterization of active power devices.

Effect of Photo Misalignment on N-LDMOS Hot Carrier Device Reliability

Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is that it can easily be integrated within existing technologies to handle a wide range of operating voltages without significant process changes. Because of the high voltages applied to the N-LDMOS device hot carrier (HC) degradation is a real reliability concern. In high power applications N-LDMOS devices are often implemented in transistor arrays where the basic cell is a dual gate single drain device. This paper focuses on understanding unusual N-LDMOS HC results in which single gate devices had significantly better HC performance than dual gate devices

Integrated Procedure Automating Test Chip Layout, Place and Route, and Test Plan Development for Efficient Parametric Device and Process Design

This work describes a novel system for device development that automates and fully integrates the workflow from test chip construction, from placement and routing to electrical test program generation. In addition to accelerating test chip and test program development, this system facilitates parameterized data analysis, thereby providing a framework that finally allows the user to realize the full benefits of complex and elegant experimental device designs. By utilizing a centralized database and eliminating parameter re-entry, the automation provided by this integrated approach eliminates many of the sources for human error while maximizing reuse between technologies.

Highly automated test chip layout and test plan development for parametric electrical test

This work outlines a fully integrated device development procedure that automates test chip development, including placement and routing algorithms, and electrical test program generation. This procedure improves over classic test chip and electrical test program development by reducing the development timeline and allowing more complete and elegant experimental device design, as well as eliminating many of the opportunities for human error while maximizing reuse between technologies.

Photo Misalignment Impact on the Hot Carrier Reliability of Lateral DMOS Devices

Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is that it can easily be integrated within existing technologies to handle a wide range of operating voltages without significant process changes. Because of the high voltages applied to the N-LDMOS device hot carrier (HC) degradation is a real reliability concern. In high power applications N-LDMOS devices are often implemented in transistor arrays where the basic cell is a dual gate single drain device. This paper focuses on understanding unusual N-LDMOS HC results in which single gate devices had significantly better HC performance than dual gate devices.