Anil Thakoor

Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips

Evolvable hardware (EHW) addresses on-chip adaptation and self-configuration through evolutionary algorithms. Current programmable devices, in particular the analog ones, lack evolution-oriented characteristics. This paper proposes an evolution-oriented field programmable transistor array (FPTA), reconfigurable at transistor level. The FPTA allows evolutionary experiments with reconfiguration at various levels of granularity. Experiments in SPICE simulations and directly on a reconfigurable FPTA chip demonstrate how the evolutionary approach can be used to automatically synthesize a variety of analog and digital circuits.

Evolution of analog circuits on field programmable transistor arrays

Evolvable Hardware (EHW) refers to HW design and self reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing also a set of selected applications. A fine-grained Field Programmable Transistor Array (FPTA) architecture for reconfigurable hardware is presented as an example of an initial effort toward evolution-oriented devices. Evolutionary experiments in simulations and with a FPTA chip in-the-loop demonstrate automatic synthesis of electronic circuits. Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing to evolvable hardware. To illustrate this situation, one demonstrates here the evolution of circuits implementing parametrical connectives for fuzzy logics. In addition to synthesizing circuits for new functions, evolvable hardware can be used to preserve existing functions and achieve fault-tolerance, determining circuit configurations that circumvent the faults. In addition, we illustrate with an example how evolution can recover functionality lost due to an increase in temperature. In the particular case of space applications, these characteristics are extremely important for enabling spacecraft to survive harsh environments and to have long life.

Analog 3-D Neuroprocessor for Fast Frame Focal Plane Image Processing

A particularly challenging neural network application requiring high-speed and intensive image processing capability is target acquisition and discrimination. It requires spatio-temporal recognition of point and resolved targets at high speeds. A reconfigur able neural architecture may discriminate targets from clutter or classify targets once resolved. By mating a 64 x 64 pixel array infrared (IR) image sensor to a 3-D stack (cube) of 64 neural-net ICs along respective edges, every pixel would directly input to a neural network, thereby processing the infor-mation with full parallelism. Being mated to the infrared sensor array, the cube would operate at 90°K temperature with <250 nanosecond signal processing speed and a low power consumption of only -2 watts. For low power and compactness in hardware, the emphasis has been on parallelism and analog signal processing. A versatile reconfigurable circuit is presented that offers a variety of neural architectures: multilayer perceptron, template matching with winner-take-all (WTA) circuitry, and a new architecture of cascade backpropagation (CBP). Special designs of analog neuron and synapse implemented in VLSI are presented which bear out high speed response both at room and low temperatures with synapse-neuron signal propagation times of ∼100 ns. The CBP learning algorithm is illustrated by solving in simulation the nonlinear 6-bit parity problem. Results show that this algorithm is robust even with synaptic resolutions limited to 5 bits. Therefore, it is particularly suitable for hardware implementation.

Optically addressed ferroelectric memory with nondestructive readout

We present a review of the emerging optically addressed ferroelectric memory with nondestructive readout as a nonvolatile memory technology, identify its high-impact applications, and project on some novel device designs and architectures that will enable its realization. Based on the high-speed bidirectional polarization-dependent photoresponse, simulation of a readout circuit for a 16-kbit VLSI ferromemory chip yields read-access times of ~20 ns and read-cycle times of ~30 ns (~34 ns and ~44 ns, respectively, within a framework of a radiation-hard environment), easily surpassing those of the conventional electrical destructive readout. Extension of the simulation for a 64-kbit memory shows that the read-access and -cycle times are only marginally increased to ~21 ns and ~31 ns, respectively (~38 ns and ~48 ns, with a radiation-hard readout circuitry). Commercial realization of the optical nondestructive readout, however, would require a reduction in the incident (optical) power by roughly an order of magnitude for the readout or an enhancement in the delivered power-to-size ratio of semiconductor lasers for compact implementation. We present a new two-capacitor memory-cell configuration that provides an enhanced bipolar optoelectronic response from the edges of the capacitor at incident power as low as ~ 2 mW/µm(2). A novel device design based on lead zirconate titanate with the c axis parallel to the substrate is suggested to reduce the requirement of incident optical power further by orders of magnitude.

Speed enhancement with soft computing hardware

During the past few years JPL has been actively involved in soft computing research encompassing theory, architecture, and electronic hardware. There are a host of soft computing applications that require orders of magnitude enhancement in speed compared to present day simulations on digital machines. For real-time computing this is made possible by selecting suitable algorithms, designing compatible architectures and implementing them in parallel processing hardware. A compact low-power hardware design for in-situ applications uses a 3D-packaged artificial neural network (ANN) multi-chip module performing object classification and recognition with 1012 multiply-sum operations per second (ops). Additionally, development on evolvable hardware (EHW) implemented on reconfigurable electronic hardware has shown exciting high-speed evolution of various digital and analog circuits. We review our work to demonstrate real-time processing.