Sabrina E. Kemeny

CMOS active pixel image sensors for highly integrated imaging systems

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-/spl mu/m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 /spl mu/m/spl times/40 /spl mu/m with 26% fill-factor. Array sizes of 28/spl times/28 elements and 128/spl times/128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 /spl mu/V/e/sup -/ for the p-well devices and 6.5 /spl mu/V/e/sup -/ for the n-well devices. Input referred read noise of 28 e/sup -/ rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed.

128 x 128 CMOS photodiode-type active pixel sensor with on-chip timing, control, and signal chain electronics

A 128 X 128 element CMOS active pixel image sensor (APS) with on-chip timing, control, and signal chain electronics has been designed, fabricated and tested. The chip is implemented in 1.2 micrometers n-well process with a 19.2 micrometers pixel pitch. The sensor uses a photodiode-type CMOS APS pixel with in-pixel source follower, row selection and reset transistors. The sensor operates from a +5 V supply and requires only a clock signal to produce video output. The chip performs correlated double sampling (CDS) to suppress pixel fixed pattern noise, and double delta sampling (DDS) to suppress column fixed pattern noise. The on-chip control circuitry allows asynchronous control of an inter frame delay to adjust pixel integration. On-chip control is also provided to select the readout of any size window of interest.

Multiresolution image sensor

The development of the CMOS active pixel sensor (APS) has, for the first time, permitted large scale integration of supporting circuitry and smart camera-functions on the same chip as a high-performance image sensor. This paper reports on the demonstration of a new 128/spl times/128 CMOS APS with programmable multiresolution readout capability. By placing signal processing circuitry on the imaging focal plane, the image sensor can output data at varying resolutions which can decrease the computational load of downstream image processing. For instance, software intensive image pyramid reconstruction can be eliminated. The circuit uses a passive switched capacitor network to average arbitrarily large neighborhoods of pixels which can then be read out at any user-defined resolution by configuring a set of digital shift registers. The full resolution frame rate is 30 Hz with higher rates for all other image resolutions. The sensor achieved 80 dB of dynamic range while dissipating only 5 mW of power. Circuit error was less than -34 dB and introduced no objectionable fixed pattern noise or other artifacts into the image.

Programmable multiresolution CMOS active pixel sensor

CMOS active pixel sensors (APS) allow the flexibility of placing signal processing circuitry on the imaging focal plane. The multiresolution CMOS APS can perform block averaging on-chip to eliminate the off-chip software intensive image processing. This 128 X 128 APS array can be read out at any user-defined resolution by configuring a set of digital shift registers. The full resolution frame rate is 30 Hz with higher rates for all other image resolutions.

CMOS active pixel image sensor with simple floating gate pixels

A new pixel structure using a simple floating gate (SFG) has been proposed. The pixel consists of a coupling capacitor, a photogate, a barrier gate and a MOS transistor. It features complete reset that results in no kTC noise and no image lag, high blooming overload protection, nondestructive readout (NDRO), and CMOS compatibility. Its basic operation has been confirmed with a 32(H)/spl times/27(V) pixel area array. Since the pixel structure is relatively simple, small pixel size is feasible. >

Update on focal-plane image processing research

An update on research activities at Columbia University in the area of focal-plane image processing is presented. Two thrust areas have been pursued: image reorganization for image compression and image half-toning. The image reorganization processor is an integration of a 256 X 256 frame-transfer CCD imager with CCD-based circuitry for pixel data reorganization to enable difference encoding for hierarchical image compression. The reorganization circuitry occupies 2 of the total chip area and is performed using three parallel-serial-parallel (SP3) registers, a pixel resequencing block, and a sampling block for differential output. The chip has achieved a CTE of 0.99994 in this new SP3 architecture, at an output rate of 83 X 103 pixels/sec. (0.9996 at 2 X 106 pixels/sec) and an overall output amplifier sensitivity of 3.2 (mu) V/electron. The half-toning chip design has been described previously, and consists of a 256 X 256 frame transfer imager, a pipeline register, and comparator circuit. Functional testing of these elements is reported at this time.

Progress in CMOS Active Pixel Image Sensors

Recent research results regarding the investigation of CMOS active pixel image sensors (APS) are reported. An investigation of various designs for the pixel, including photogate devices of various geometries and photodiode devices, has been performed. Optoelectronic performance including intrapixel photoresponse maps taken using a focused laser scanning apparatus are presented. Several imaging arrays have also been investigated. A 128 X 128 image sensor has been fabricated and characterized. Both p-well and n-well implementations have been explored. The demonstrated arrays use 2 micrometers CMOS design rules and have a 40 X 40 micrometers pixel pitch. Typical design fill-factor is 26%. Output sensitivity is 3.7 (mu) V/e- for the p-well devices and 6.5 (mu) V/e- for the n-well devices. Read noise is less than 40 e- rms for the baseline designs. Dynamic range has been measured to be over 71 dB using a 5 V supply voltage. The arrays are random access with TTL control signals. Results regarding on-chip suppression of fixed pattern noise also are presented.

CCD focal-plane image reorganization processors for lossless image compression

Four image reorganization ICs that enable real-time difference encoding for hierarchical lossless image compression are reported. Two image reorganization processors are realized on the focal-plane and two are designed for hybridization to a separate imager IC. The two focal-plane ICs represent the first integration of a 256*256 buried-channel frame-transfer CCD image sensor with additional charge-domain circuitry to enable image reformatting at video rates (28 frames/s). The four ICs generate pyramidal pixel output in 3*3 blocks with the center pixel first. Pixel data reorganization is performed through simultaneous readout of three rows of data, followed by pixel resequencing and sampling to provide differential output. A novel architecture provides simultaneous readout of multiple imager rows on the focal-plane ICs. The ICs have achieved a charge-transfer efficiency (CTE) of 0.99996 in the conventional horizontal and vertical CCD registers, and a CTE of 0.99994 in the SP/sup 3/ registers. >

Parallel Processor Array For High Speed Path Planning

The first integration of a 24 x 25 array of processors for high speed optimal path planning is reported. Based on programmed terrain costs (traversal time), the IC determines, in parallel, the fastest routes from a selected starting point(s) to all other points on a given tcrrain. The chip has hQen successfully tested at a 7 MHz clock frequency, with typical path determination requiring 230 lis, resulting in a four order of magnitude speed-up over currmt sofhvare-hasQd shortmtroute techniques.

Analog 3-D Neuroprocessor for Fast Frame Focal Plane Image Processing

A particularly challenging neural network application requiring high-speed and intensive image processing capability is target acquisition and discrimination. It requires spatio-temporal recognition of point and resolved targets at high speeds. A reconfigur able neural architecture may discriminate targets from clutter or classify targets once resolved. By mating a 64 x 64 pixel array infrared (IR) image sensor to a 3-D stack (cube) of 64 neural-net ICs along respective edges, every pixel would directly input to a neural network, thereby processing the infor-mation with full parallelism. Being mated to the infrared sensor array, the cube would operate at 90°K temperature with <250 nanosecond signal processing speed and a low power consumption of only -2 watts. For low power and compactness in hardware, the emphasis has been on parallelism and analog signal processing. A versatile reconfigurable circuit is presented that offers a variety of neural architectures: multilayer perceptron, template matching with winner-take-all (WTA) circuitry, and a new architecture of cascade backpropagation (CBP). Special designs of analog neuron and synapse implemented in VLSI are presented which bear out high speed response both at room and low temperatures with synapse-neuron signal propagation times of ∼100 ns. The CBP learning algorithm is illustrated by solving in simulation the nonlinear 6-bit parity problem. Results show that this algorithm is robust even with synaptic resolutions limited to 5 bits. Therefore, it is particularly suitable for hardware implementation.