Bibhas Manna

Spatial Composition Grading of Binary Metal Alloy Gate Electrode for Short-Channel SOI/SON MOSFET Application

An overall performance comparison analysis based on 2-D Poissons equation solution has been presented here both for silicon-on-insulator (SOI) and silicon-on-nothing (SON) MOSFET structures. In this paper, for the first time, an idea of work function engineering with continuous horizontal mole fraction variation in a binary alloy gate has been proposed and implemented analytically to reduce rolloff in threshold voltage for SON MOSFET, thereby improving its performance over single-gate SON structures. Analytical model-based simulation verified that SON is superior over SOI MOSFET due to its higher immunity to different short-channel effects and increased current driving capability. Our results are found to be in good agreement with simulation results, thereby verifying the accuracy of the proposed analytical model.

Small - signal parameter extraction to study the RF performance of SOI and SON MOSFET

A simple small-signal equivalent circuit for generalized horizontal SOI and SON MOSFET has been presented. The intrinsic parameters of the small-signal model are obtained from a compact capacitance based analytical model Using those small-signal model parameters, frequency dependent performances of those structures are simulated with SILVACO SMART SPICE RF Module. It has been realized that SON technology improves the frequency response due to improved conductance and reduced parasitic effects. This type of combined analytical and simulation approach allows us to predict the technology road map for future ultra dense, low power nanoelectronics devices and their efficiency in RF frequency range.