Anindya Nath

Achieving clean epitaxial graphene surfaces suitable for device applications by improved lithographic process

It is well-known that the performance of graphene electronic devices is often limited by extrinsic scattering related to resist residue from transfer, lithography, and other processes. Here, we report a polymer-assisted fabrication procedure that produces a clean graphene surface following device fabrication by a standard lithography process. The effectiveness of this improved lithography process is demonstrated by examining the temperature dependence of epitaxial graphene-metal contact resistance using the transfer length method for Ti/Au (10 nm/50 nm) metallization. The Landauer-Buttiker model was used to explain carrier transport at the graphene-metal interface as a function of temperature. At room temperature, a contact resistance of 140 Ω-μm was obtained after a thermal anneal at 523 K for 2 hr under vacuum, which is comparable to state-of-the-art values.

Microwave Annealing of Very High Dose Aluminum-Implanted 4H-SiC

A microwave heating technique has been used for the electrical activation of Al+ ions implanted in semi-insulating 4H-SiC. Annealing temperatures in the range of 2000–2100 °C and annealing time of 30 s have been used. The implanted Al concentration has been varied from 5×1019 to 8×1020 cm-3. A minimum resistivity of 2×10-2 Ωcm and about 70% electrical activation of the implanted Al have been measured at room temperature for an implanted Al concentration of 8×1020 cm-3 and microwave annealing at 2100 °C for 30 s.

Impact of surface treatments on high-κ dielectric integration with Ga-polar and N-polar GaN

Gallium- and nitrogen-polar GaN surfaces are subjected to a variety of pretreatments, including oxidation, before the application of high-κ dielectrics by atomic layer deposition (ALD) in order to assess the “best” preparation of smooth, clean, and electrically high-performing dielectric semiconductor interfaces. In terms of topographical and chemical cleanliness, a pretreatment with a wet chemical piranha etch (H2SO4:H2O2) was found to be optimum for both surfaces, and additionally, (NH4)2S is effective for N-polar surfaces. Both thermal and plasma oxidations were employed for controlled growth of native oxides. For Ga-polar surfaces, all native oxides were as smooth as pretreated surfaces, while for N-polar surfaces, all native oxides are much rougher except for very short, high temperature oxidations. ALD Al2O3 films on Ga-polar surfaces are smoother for pretreated surfaces than for as-received surfaces, whereas for N-polar surfaces the opposite is true. In general, ALD HfO2 films on Ga-polar surfaces ...

Microwave Annealing of High Dose Al+-implanted 4H-SiC: Towards Device Fabrication

High-purity semi-insulating 8° off-axis 〈0001〉 4H-SiC was implanted with Al+ at different doses and energies to obtain a dopant concentration in the range of 5 × 1019–5 × 1020 cm−3. A custom-made microwave heating system was employed for post-implantation annealing at 2,000 °C for 30 s. Sheet resistance and Hall-effect measurements were performed in the temperature range of 150–700 K. At room temperature, for the highest Al concentration, a minimum resistivity of 3 × 10−2 Ω cm was obtained, whereas for the lowest Al concentration, the measured resistivity value was 4 × 10−1 Ω cm. The onset of impurity band conduction was observed at around room temperature for the samples implanted with Al concentrations ≥3 × 1020 cm−3. Vertical p+-i-n diodes whose anodes were made by 1.5 × 1020 cm−3 Al+ implantation and 2,000 °C/30 s microwave annealing showed exponential forward current–voltage characteristics with two different ideality factors under low current injection. A crossover point of the temperature coefficient of the diode resistance, from negative to positive values, was observed when the forward current entered the ohmic regime.

Improving Doping Efficiency of P+ Implanted Ions in 4H-SiC

An inductively heated furnace and an ultra-fast microwave heating system have been used for performing post implantation annealing processes of P+ implanted semi-insulating <0001> 4H SiC at 1800-1950°C for 5 min and 2000-2050°C for 30 s, respectively. Very high P+ implantation fluences in the range 71019 81020 cm-3 have been studied. The annealing processes in the inductive furnace and the one at the lower temperature in the microwave furnace show a saturation in the efficiency of the electrical activation of the implanted P+ that is bypassed by the microwave annealing process at the higher temperature. The measured electron mobility values versus electron density are elevated in all the studied samples and for every post implantation annealing process. This has been ascribed to an elevated implanted crystal recovery due to the very high annealing temperatures > 1800°C.

Microwave Annealing of Al+ Implanted 4H-SiC: Towards Device Fabrication

Carrier transport in Al+ implanted 4H-SiC for Al concentrations in the 5 × 1019 5 × 1020 cm-3 range and after 2000°C/30s microwave annealing are characterized. Each sample resistivity decreases with increasing temperature and attains values of about 102 Ωcm for temperatures > 600 K. At room temperature, resistivity decreases from 4 × 10-1 Ωcm to 3 × 102 Ωcm with the increase of implanted Al concentration. The onset of an impurity band conduction around room temperature takes place for implanted Al concentrations > 3 × 1020 cm-3. Al+ implanted and microwave annealed 4HSiC vertical p+-i-n diodes have shown promising forward characteristics.

Universal conformal ultrathin dielectrics on epitaxial graphene enabled by a graphene oxide seed layer

The amphiphilic nature of graphene oxide (GO) is exploited as a seed layer to facilitate the ultrathin and conformal high-κ metal oxide (MOX) deposition on defect-free epitaxial graphene (EG) by atomic layer deposition (ALD). Three different high-κ metal oxides (Al2O3, HfO2 and TiO2) with various thicknesses (4–20 nm) were grown on ultrathin (1.5 nm) GO seed layers on EG. The quality of such dielectrics was examined by fabricating various metal-insulator-graphene (MIG) type devices. For MIG tunnel devices, on-off ratios of 104 and 103 were obtained for 4 nm Al2O3 and HfO2 dielectric layers, respectively. Additionally, no defect/trap assisted conduction behavior was observed. Graphene field effect transistors (GFETs) with bi-layer metal oxide stack (6 nm TiO2/14 nm HfO2) demonstrated a peak on-state current of 0.16 A/mm, an on-resistance of 6.8 Ω mm, an Ion/Ioff ratio of ∼4, and a gate leakage current below 10 pA/mm at Vds = 1 V and Vgs = 4 V. Capacitance-voltage measurement of the same GFETs exhibited a l...

Post-Growth Reduction of Basal Plane Dislocations by High Temperature Annealing in 4H-SiC Epilayers

Basal Plane Dislocations (BPD) were reduced in 4H-SiC epilayers by high temperature annealing in the range of 1600 °C to 1950 °C using two annealing techniques. Samples annealed at > 1750 °C showed almost complete elimination of BPDs propagating from the substrate. However, surface morphology was degraded for MW annealed samples above 1800 °C, with new BPDs being generated from the surface. A new capping technique was developed along with application of high N2 overpressure to preserve the surface morphology and avoid formation of new BPDs.

Temperature dependent current-voltage characteristics of microwave annealed Al + implanted 4H-SiC p + -i-n diodes

In this work the temperature dependent current-voltage characteristics of microwave annealed 4H-SiC vertical p+-i-n diodes are studied to identify some of the traps which affect the generation-recombination current of these diodes.

Fully Ion Implanted Vertical p-i-n Diodes on High Purity Semi-Insulating 4H-SiC Wafers

The fabrication of a fully ion-implanted and microwave annealed vertical p-i-n diode using high purity semi-insulating 4H-SiC substrate has been demonstrated for the first time. The thickness of the intrinsic region is the wafer thickness 350 µm. The anode and cathode of the diode have been doped with Al and P, respectively, to concentrations of few times 1020 cm-3 by ion implantation. The post implantation annealing has been performed by microwave heating the samples up to 2100°C. The device rectifying behavior indicates that a carrier modulation takes place in the bulk intrinsic region.