Anjan Kumar

Designing of Power Efficient ROM Using LVTTL and Mobile-DDR IO Standard on 28nm FPGA

This paper contains designing of energy efficient memory circuit using two different IO standard i.e. LVTTL and Mobile-DDR on 28nm (Artix-7) Field Programmable Gate Array. We are using Xilinx ISE simulator version 14.2, Verilog hardware description language and Artix-7 FPGA. The design has been tested at different operating frequencies of Latest Intel processor that are at Intel I-3, Intel I-5 and Intel I-7 to check the compatibility of the design with processors available in the market and to find most efficient IO standard at different operating frequencies.

Diode Based Trimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

In this paper a high performance diode based trimode Multi-Threshold CMOS (MTCMOS) technique is introduced which minimizes standby leakage current and provides a better way to control the ground bounce noise during sleep to active mode transition using one additional mode i.e. hold mode. Analysis of trimode MTCMOS technique using low power 16-bit full adder has been done for reduction of standby leakage current and ground bounce noise. Further, to evaluate the effectiveness of diode based trimode Multi-Threshold CMOS technique, simulation has been done on low power 16-bit full adder circuit with BPTM 90nm technology at room temperature with supply voltage of 1 V. Diode based trimode Multi-Threshold CMOS technique reduces ground bounce noise by 89.36% and standby leakage current by 19.24% as compared to the standard trimode MTCMOS technique.

Stacked transistor based multimode power efficient MTCMOS full adder design in 90nm CMOS technology

High rate of power consumption in the digital integrated circuit is the major field of concern in the development of VLSI circuits. Demand of higher speed, multiple operations and smaller process geometry contributes in the leakage power. So today leakage power consumption is the most important source of power dissipation rather than run time power consumption. Previously many techniques have been proposed for the leakage reduction. Amongst all MTCMOS technique carries the property of being most efficient in leakage reduction. In this paper we are going to analyze the different types of low power adder circuits with different types of low power design methodologies. The comparison results have also been displayed in this paper. The circuits are simulated in 90nm CMOS technology using tanner EDA simulator.

Simulation and Verification of Voltage and Capacitance Scalable 32-bit Wi-Fi Ah Channel Enable ALU Design on 40nm FPGA

In this paper, Wi-Fi ah channel enable 32-bit ALU on 40nm based Virtex-6 FPGA is designed using voltage scaling and capacitance scaling. It is Wi-Fi ah channel enable because we are operating our ALU with frequency of 0.9 GHz which is the frequency of ah Wi-Fi channel estimated to be released in 2016. We are analyzing effect of voltage scaling and capacitance scaling which are two of the different factors responsible for variation in power dissipation. We operated our ALU at 0.9 GHz at different voltages by also using capacitance scaling. Then we also analysed our design to work on different voltages irrespective of capacitances. In this Verilog is used as Hardware Description Language and XPower Analyser for Power calculation and Xilinx ISE Design Suite 14.2 as simulator.

Design of Low Noise Low Power Two Stage CMOS Operational Amplifier Using Equivalent Transistor Replacement Technique for Health Monitoring Applications

The recent interest of mankind on various personal and real time health monitoring system has accelerated the demand for more efficient and advanced biomedical devices. Physiological signals are comparatively weaker in magnitude (few μV to few mV) and also exhibit lower frequencies. Therefore a low power, low input-referred noise analog front end circuitry is to be designed for filtering and amplifying the biopotential signals before digitizing it. A design methodology using the Equivalent Transistor Replacement Technique (ETRT) for low power and low noise Two Stage Operational Amplifier is the front end circuitry of Biopotential Signal Acquisition System. For providing high output swing a Common Source stage is connected at the output and for the reduction of the input-referred noise a differential PMOS input stage is used. The designed circuit of Op-Amp gives a gain of 61 dB, power consumption 60μw, input-referred noise 37nV/sqHz and bandwidth 20.1 KHz for the 60μA external bias current.

Design of low noise low power biopotential tunable amplifier using voltage controlled pseudo-resistor for biosignal acquisition applications

The development of the large scale multi-electrode neural-recording systems has accelerated the process of brain monitoring. Neural amplifier is the most important development in this field. A fully integrated low-noise tunable neural amplifier is presented in this paper. The proposed neural amplifier not only provides low signal distortion and high output swing but also ensures good linearity over the entire frequency band of interest. Tunability of the resistance is obtained with the help of variable Vref. The amplifier is designed in standard 90nm CMOS process technology using 1V supply voltage. The simulated result shows an input-referred noise of 1.2μVrms to 0.05μVrms for the frequency range of 5.2 Hz to 540 KHz. A noise efficiency factor (NEF) of 2.89, with full output swing is obtained.

Forward Body Biased Multimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

As technology is continuously scaling down leakage current is increasing exponentially. Multi-Threshold CMOS technique is a well known way to reduce leakage current but it gives rise to a new problem i.e. ground bounce noise which reduces the reliability of the circuit and because of this circuit may incorrectly switch to the wrong value or may switch at the wrong time. Ground bouncing noise produced during sleep to active mode transitions is an important challenge in Multi-Threshold CMOS (MTCMOS) circuits. The effectiveness of noise-aware forward body biased multimode MTCMOS circuit techniques to deal with the ground bouncing noise is evaluated in this paper. An additional wait mode is investigated to gradually dump the charge stored on the virtual ground line to the real ground distribution network during the sleep to active mode transitions. The peak amplitude of the ground bouncing noise is reduced by 93.28% and standby leakage current is reduced by 23.94% as compared to standard trimode MTCMOS technique. To evaluate the significance of the proposed multimode Multi-Threshold CMOS technique, the simulation has been performed for 16-bit full adder circuit using BPTM 90nm standard CMOS technology at room temperature with supply voltage of 1V .