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Dive into the research topics where Hervé Le-Gall is active.

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Featured researches published by Hervé Le-Gall.


2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW) | 2016

Mostly-digital design of sinusoidal signal generators for mixed-signal BIST applications using harmonic cancellation

Hani Malloug; Manuel J. Barragan; Salvador Mir; Emmanuel Simeu; Hervé Le-Gall

This work proposes a novel approach for the design of high-quality on-chip sinusoidal signal generators using digital circuitry. The proposed generation technique is based on a simple digital shift-register that provides a set of phase-shifted versions of a digital square-wave signal. These square-wave signals are conveniently combined using a harmonic cancellation strategy to yield a spectrally pure sinusoidal output signal. The proposed strategy allows cancelling low-frequency harmonics close to the fundamental component of the generated sinusoidal signal, while a simple first order low-pass filter is used to attenuate higher order harmonic components. A simple one-shot calibration strategy is also presented in order to compensate the effects of the main non-idealities affecting the dynamic linearity of the generator. Statistical behavioral simulations are provided to demonstrate the feasibility of the proposed generator.


Journal of Electronic Testing | 2016

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

Guillaume Renaud; Manuel J. Barragan; Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le-Gall; Hervé Naudet

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor-level and behavioral-level simulations that employ actual production test data.


IEEE Design & Test of Computers | 2016

Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques

Manuel J. Barragan; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le-Gall; Neha Bhargava; Ankur Bal

Accurate and efficient evaluation of alternative test methods is required for analog/mixed-signal circuits. To address this need, this article presents a semiautomated practical simulation flow specifically targeting circuits with long simulation times.


Archive | 2007

Estimating of the jitter of a clock signal

Hervé Le-Gall


Archive | 2011

CIRCUITRY FOR BUILT-IN SELF-TEST

Hervé Le-Gall


Archive | 2011

METHOD AND DEVICE FOR ANALYZING THE BEHAVIOR OF A POWER SUPPLY IN A CIRCUIT

Hervé Le-Gall


Archive | 2011

METHOD AND DEVICE FOR ESTIMATING PARAMETERS OF A SYSTEM FOR SPREADING THE SPECTRUM OF A CLOCK SIGNAL

Hervé Le-Gall


Archive | 2013

CHARACTERIZATION OF THE JITTER OF A CLOCK SIGNAL

Hervé Le-Gall


Archive | 2013

DIGITAL SERIAL MULTIPLIER

Hervé Le-Gall


Archive | 2011

BUILT-IN SELF-TEST CIRCUITRY

Hervé Le-Gall

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Manuel J. Barragan

Centre national de la recherche scientifique

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Salvador Mir

Centre national de la recherche scientifique

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Emmanuel Simeu

Centre national de la recherche scientifique

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Guillaume Renaud

Centre national de la recherche scientifique

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