Anne E. Gattiker

Current signatures: application

Analysis of IC technology trends indicates that Iddq testing may be approaching its limits of applicability. The new concept of the current signature may expand this limit under the condition that an appropriate current-signature-based test methodology is developed. This paper is a first step toward such a goal. It is focused on current signature step detection in a noisy test environment. Application of current signatures in die selection and defect diagnosis is discussed as well.

Deformations of ic structure in test and yield learning

Abstract This paper argues that the existing approaches to modelingand characterization of IC malfunctions are inadequate fortest and yield learning of Deep Sub-Micron (DSM) products.Traditional notions of a spot defect and local and global pro-cess variations are analyzed and their shortcomings areexposed. A detailed taxonomy of process-induced deforma-tions of DSM IC structures, enabling modeling and charac-terization of IC malfunctions, is proposed. The blueprint of aroadmap enabling such a characterization is suggested. Keywords : yield learning, fault modeling, defects, diagno-sis, defect characterization. 1 Introduction The motivation, purpose and overall structure of this paperhave already been explained in the abstract above. The dis-cussion of the prior and relevant publications should be thenext natural component of this paper. But it is skipped aswell, even if there exists substantial body of relevant publi-cations in the related domain (some of them are listed as ref-erences in [1,2].) It is skipped to avoid unnecessarydiscussion of the weaknesses of related results presented inthe past. Simply, majority of published papers with the ICtechnology-oriented flavour (and prime examples are the fol-lowing papers co-written by the first author of this paper [3,4, 5, 6, 7, 8]) do not offer sufficient insight into failure mech-anisms to address challenges posed by the DSM era prod-ucts. A substantial portion of this paper attempts to justify theabove, somewhat provocative claim. Then the remainingportion of the paper is used to suggest directions of theresearch, which we should undertake to truly assist test andyield learning of modern era ICs.

To DFT or not to DFT

Despite a substantial amount of prior work in design-for-testability (DFT) cost modeling, the decision whether or not and how to use DFT is still not an easy one. The problem is that the relationship between DFT benefits and costs are still far from being well understood. The objective of this paper is to study the DFT decision-making process and to identify its missing or weak links. The first step of this study involved development of a new DFT cost/benefit trade-off modeling procedure. Next, the developed cost model (which we call the CMU Test Cost model) was used, with a range of parameters representing typical industrial conditions, to answer the question: to DFT or not to DFT. The obtained results indicate that in the DFT application space there exist regions in which one can provide a clear answer to this question. There also exist regions of uncertainty. One of the objectives of our study has been to identify ways of minimizing this uncertain region.

Current signatures for production testing [CMOS ICs]

The concept of the current signature has been proposed as a means for improving testing resolution over single-threshold Iddq testing. This paper postulates a practical methodology for applying the current signature concept for die selection in a production environment.

Smart-substrate multichip-module systems

This implementation strategy enables incremental test of all system components, providing an alternative solution to the known good die testing problem. The authors present a simple microcontroller emulator designed and fabricated for study of the test logic needed as a key component of this method.<<ETX>>

Smart Substrate MCMs

This paper presents a cost-based assessment of the effectiveness of Smart Substrate MCM Systems. A Smart Substrate MCM System is one in which the substrate contains active circuitry for carrying out testing functions. The feasibility of using this approach is investigated. The Smart Substrate strategy is compared to an alternative approach based on the assumption that system components are perfect (“Known Good Die (KGD)” approach). The obtained results identify the domain of applicability of Smart substrate MCMs and point to limitations of the KGD approach.