Pranab K. Nag

Hierarchical extraction of critical area for shorts in very large ICs

This paper describes an algorithm for efficiently extracting critical area in large VLSI circuits. The algorithm, implemented to handle shorts between electrical nets, takes advantage of the available hierarchy in the layout description in order to speed-up computation and minimize memory usage. The developed software-CREST-was tested for a spectrum of actual IC designs and was found very efficient as compared to existing techniques.

To DFT or not to DFT

Despite a substantial amount of prior work in design-for-testability (DFT) cost modeling, the decision whether or not and how to use DFT is still not an easy one. The problem is that the relationship between DFT benefits and costs are still far from being well understood. The objective of this paper is to study the DFT decision-making process and to identify its missing or weak links. The first step of this study involved development of a new DFT cost/benefit trade-off modeling procedure. Next, the developed cost model (which we call the CMU Test Cost model) was used, with a range of parameters representing typical industrial conditions, to answer the question: to DFT or not to DFT. The obtained results indicate that in the DFT application space there exist regions in which one can provide a clear answer to this question. There also exist regions of uncertainty. One of the objectives of our study has been to identify ways of minimizing this uncertain region.

CAD at the design-manufacturing interface

Owing to rapid changes of IC technologies, traditionaldesign rule checking is becoming inadequate to assure satisfactorylevels of IC manufacturability. This paper describes a newcomputer supported design analysis environment that improvesthe efficiency of manufacturability assessment of new products.This environment, called MAPEX 2, is described in the paperalong with some of its key procedures and algorithms. Illustrationsof MAPEX 2 applications and performance figures are provided as well.

AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout

This paper describes the AFFCCA (Accurate, Fast, Flexible Computation of Critical Area) tool. The algorithms implemented in AFFCCA can handle arbitrary geometry, defects causing shorts of arbitrary shapes, and a spectrum of process induced layout deformations. The presented results indicate that the unique features of AFFCCA allow for significant improvements in the accuracy of critical area computations.

Simulation of yield/cost learning curves with Y4

This paper describes a prototype of a discrete event simulator-Y4 (yield forecaster)-capable of simulating defect related yield loss and manufacturing cost as a function of time, for a multiproduct IC manufacturing line. The methodology of estimating yield and cost is based on mimicking the operation and characteristics of a manufacturing line in the time domain. The paper presents a set of models that take into account the effect of particles introduced during wafer processing as well as changes in their densities due to process improvements. These models also illustrate a possible way of accounting for the primary attributes of fabrication, product, and failure analysis which affect yield learning. A spectrum of results are presented for a manufacturing scenario to demonstrate the usefulness of the simulator in formulating IC manufacturing strategies.

Testability-oriented channel routing

The quality of IC testing can be improved by applying appropriate design strategies. In this paper, we present a testability-oriented routing methodology, which can be used to modify the IC layout so as to reduce the probability of test escape. A testability-oriented iterative channel routing tool based on this methodology has been developed. Example applications of this tool illustrating the methodology are also presented in the paper.

Cost based tradeoff analysis of standard cell designs

In this paper, we propose a methodology for estimation of chip area, yield and eventually cost of a standard cell design as a function of number of metal layers. Given a placement of the design, a measure of metal utilization distribution is produced which, in turn, is used to predict die size and the yield for an analyzed design. This method is applied to a variety of small standard cell designs with the application of cost model [22] developed for 0.25 micron CMOS process, to calculate die costs. It is claimed that such a prediction technique, as proposed in this paper, is a necessary element of modern IC design flow.

Design-manufacturing interface. I. Vision [VLSI]

This paper proposes a vision for a new research domain emerging on the interface between design and manufacturing of VLSI circuits. The key objective of this domain is the minimization of the mismatch between design and manufacturing which is rapidly growing with the increase in complexity of VLSI designs and IC technologies. This broad objective is partitioned into a number of specific tasks. Often, one of the most important tasks is the extraction of VLSI design attributes that may be relevant from a manufacturing efficiency standpoint. The second task is yield analysis performed to detect process and design attributes responsible for inadequate yield. This paper postulates both, an overall change in the design-manufacturing interface, as well as a methodology to address the growing design-manufacturing mismatch. Attributes of a number of tools needed for this purpose are discussed as well.

Design-manufacturing interface. II. Applications [VLSI]

For pt. I see ibid., p. 550-6 (1998). This paper illustrates via examples problems at the design-manufacturing interface that exist in the IC industry today, and the ability of the YAN/PODEMA framework in solving these problems. The need for further development of the framework is also emphasized.

DFM Evaluation Using IC Diagnosis Data

Design for manufacturability rule evaluation using manufactured silicon (DREAMS) is a comprehensive methodology for evaluating the yield-preserving capabilities of a set of design for manufacturability (DFM) rules using the results of logic diagnosis performed on failed ICs. DREAMS is an improvement over prior art in that the distribution of rule violations over the diagnosis candidates and the entire design are taken into account along with the nature of the failure (e.g., bridge versus open) to appropriately weight the rules. Silicon and simulation results demonstrate the efficacy of the DREAMS methodology. Specifically, virtual data is used to demonstrate that the DFM rule most responsible for failure can be reliably identified even in light of the ambiguity inherent to a nonideal diagnostic resolution, and a corresponding rule-violation distribution that is counter-intuitive. We also show that the combination of physically aware diagnosis and the nature of the violated DFM rule can be used together to improve rule evaluation even further. Application of DREAMS to the diagnostic results from an in-production chip provides valuable insight in how specific DFM rules improve yield (or not) for a given design manufactured in particular facility. Finally, we also demonstrate that a significant artifact of DREAMS is a dramatic improvement in diagnostic resolution. This means that in addition to identifying the most ineffective DFM rule(s), validation of that outcome via physical failure analysis of failed chips can be eased due to the corresponding improvement in diagnostic resolution.