Ed van Tuijl

A 10-bit Charge-Redistribution ADC Consuming 1.9

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115×225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

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A relaxation oscillator design is described, which has a phase noise rivaling ring oscillators, while also featuring linear frequency tuning. We show that the comparator in a relaxation-oscillator loop can be prevented from contributing to 1/f2 colored phase noise and degrading control linearity. The resulting oscillator is implemented in a power efficient way with a switched-capacitor circuit. The design results from a thorough analysis of the fundamental phase noise contributions. Simple expressions modeling the theoretical phase noise performance limit are presented, as well as a design strategy to approach this limit. To verify theoretical predictions, a relaxation oscillator is implemented in a baseline 65nm CMOS process, occupying 200µm × 150µm. Its frequency tuning range is 1-12MHz, and its phase noise is L100kHz=-109dBc/Hz at fosc=12MHz, while consuming 90µW. A figure of merit of -161dBc/Hz is achieved, which is only 4dB from the theoretical limit. Copyright

W at 1 MS/s

A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and hence the input drive power is reduced by a factor 1.5 as compared to conventional sampling (CS). Considering an ideal Class A operation for the circuit driving the ADC, this translates into a minimum driver power consumption of 80μW for our ERS based ADC whereas it is 135μW for the conventional sampling, both much larger than the ADC power consumption of 3.2μW.

Towards minimum achievable phase noise of relaxation oscillators

A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the buffer circuit driving the ADC, this translates into a minimum (theoretical) driver power consumption of 50μW for our RPS based ADC whereas it is 130μW for the conventional sampling, both much larger than the ADC power consumption of 3.25μW at 1MS/s operation. Our ADC occupies an area of 0.08 mm2 and achieves an SFDR of 64 dB, an SNDR of 55 dB with a Walden Figure of Merit, FoMw of 6.8fJ/conversion-step at up-to 2MS/s.

An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC

This years session on Analog Techniques continues to defy simple categories. This session illustrates the diversity and vigor of modern analog circuitry. The rise of wearable devices and Internet of Things (IoT) leads to the emergence of nano-power designs of references, oscillators and many other blocks. New frontiers of precision, power, and performance are established.

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs

Out-of-band noise (OBN) is troublesome in analog circuits that process the output of a noise-shaping audio DAC. It causes slewing in amplifiers and aliasing in sampling circuits like ADCs and class-D amplifiers. Nonlinearity in these circuits also causes cross-modulation of the OBN into the audio band. These mechanisms lead to a higher noise level and more distortion in the audio band. OBN also leads to interference in the LF and MF band, compromising e.g. AM radio reception. To avoid these problems, it is desired to reduce OBN power to below -60dBFS. An active low-pass filter after the DAC output can reduce the OBN power to acceptable levels, but this solution is expensive in terms of power consumption and chip area. A FIR-DAC approach implements a 1b PWM modulator, followed by a semi-digital low-pass FIR reconstruction filter. It achieves high-end audio performance with sufficiently low OBN, but the FIR structure costs area, adds latency, and (like an analog low-pass filter) inherently limits the maximum output signal frequency. Multi-bit noise shapers employ smaller quantization steps and therefore output lower OBN. A cascaded-modulator architecture can directly be followed by an on-chip amplifier without low-pass filtering. However, with only 330 quantization levels, it still cannot achieve the desired -60dBFS OBN without additional filtering. Moreover, this approach requires complex dynamic-element matching (DEM) and inter-symbol interference (ISI) shaping mechanisms. The paper present an approach that reduces OBN to below -60dBFS with minimal increase in power and area consumption. It consists of two paths . The main path is based on the work of van Tuijl et al. (2004), containing a 128× oversampled 5b 3rd-order noise shaper, thermometer decoder and real-time DEM algorithm followed by a current DAC. Since the digital noise shaper generates negligible in-band noise products, the error signal of the noise shaper is practically equal to the OBN. This error signal is integrated (as part of the loop filter), quantized and fed to a correction path with a differentiating DAC (DIFF-DAC). This DAC inverts the integration action, obtaining unity signal transfer. The output currents of both paths are subtracted, reducing OBN significantly. Quantization noise of the correction path is shaped because the error signal is differentiated after quantization. Depending on the shape of the noise transfer function of the main DAC, the DIFF-DAC needs an over-range in order to accommodate the increased signal swing caused by the integration action. Still, area and power cost is minimal because the range of the DIFF-DAC is still only a fraction of the main DAC range.

Session 5 overview: Analog techniques: Analog subcommittee

Radio receivers and transmitters produce distortion products which are high above the noise floor. These products emanate from a combination of a low-order nonlinearity and the narrowband nature of the signal of interest. In this work, a scrambling system is proposed that can be added to a receiver, reducing these distortion products. Continuous time-domain signal manipulation is used to spread the spectral power of a narrowband signal, before it passes through nonlinear receiver circuitry. Digitally the original signal shape is reconstructed. This way, the distortion created by the nonlinearity does not result in dominant tones, improving IP2 and IP3 figures without increasing the intrinsic circuitry linearity, saving power and maintaining flexibility. This topology became possible through using new designs and topologies, which allow signal manipulation using passive components only. Additionally, a new high speed DAC design allows a voltage supply rail to be used as a sub-mV accurate reference. The concept is demonstrated using a software-radio approach, in which the sampling and buffering represents the nonlinear processing. With a 2.2Vpp, diff 100 MHz input signal, the measured distortion products are below −74 dBc. At 1.4 GHz input this number is 60.2 dBc. The scrambling hardware uses 54 mW in a 65nm CMOS process.

15.3 A 115dB-DR audio DAC with −61dBFS out-of-band noise

Chapter 4 describes the actual implementation of a high-speed time-interleaved ADC based on the design choices described in this book. Since timing calibration is hard to implement, a switch-driver circuit with low skew is introduced, such that timing calibration is not needed.

A narrow-to-wideband scrambling technique increasing software radio receiver linearity

Chapter 3 discusses the architecture of the sub-ADCs, which are used in the time-interleaved ADC. A Successive Approximation ADC (SA-ADC) can have a very good power efficiency, its sample-rate is however limited. In a conventional SA-ADC, the sample-rate is mainly limited by settling of the DAC. Overrange techniques can reduce the required DAC settling time. A new overrange technique is presented called the single-sided overrange technique. Compared to a conventional SA-ADC, it saves 58% of the settling time, and therefore it can be more energy efficient.

Implementation of a High-speed Time-interleaved ADC

This paper introduces a recursive multibit /spl Sigma//spl Delta/ architecture that enables a high effective quantizer resolution while needing only a limited number of DAC elements. The recursive architecture consists of a set of /spl Sigma//spl Delta/ modulators, whereby each stage cancels the quantization noise of the proceeding stage. Conventional DEM algorithms can be used in each stage to reduce the sensitivity to mismatch. The architecture enables a significant reduction of both the signal-band and out-of-band quantization noise power, compared to conventional multibit /spl Sigma//spl Delta/ converters.