Anne Van den Bosch

An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters

To obtain a high resolution CMOS current-steering digital-to-analog converter, the matching behavior of the current source transistors is one of the key issues in the design. At this moment, these matching properties are taken into account by the use of time consuming and CPU intensive Monte Carlo simulations. In this paper, a formula is derived that describes accurately the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time.

Solving Static and Dynamic Performance Limitations for High Speed D/A Converters

In this paper the factors determining the static and the dynamic performance of a current-steering CMOS D/A converter will be discussed. The impact of these factors will be converted in some design guidelines that have to be implemented in order to realize a D/A converter with a state-of-the-art performance.

The Impact of Statistical Design on the Area of High Performance CMOS Current-Steering D/A Converters

In this paper the design procedure is described to determine the dimensions of the unit current source transistor of a current-steering D/A converter in such a way as to minimize the total chip area and to maximize the circuit yield. Furthermore, the technology dependence of the current source area has been investigated. It can be concluded that going to deeper submicron technologies will not necessarily have a beneficial effect on the area of the current source array.

A Design Methodology for High Performance CMOS Current Steering D/A Converters

While in chapter 4 and 5, the emphasis has been put on modelling the static and the dynamic behaviour of the current steering D/A converter architecture, this chapter will cover the design flow for these circuits. In the first section of this chapter, the problem of determining the level of segmentation is addressed. In the remainder of the text, it has been assumed that a segmentation level of 0% matches a fully binary implementation and a segmentation level of 100% represents a fully unary architecture. Both an area based as a mathematically based approach to determine the segmentation degree are discussed. In the following two sections, the choice of the thermometer decoder and the switch driver are addressed. The remaining sections of this chapter describe in detail the dimensioning of all the transistors in the unit current cell (the switch, current source and cascode transistors).

Transistor Mismatch: Evolution and Relevance

Measuring the electrical characteristics of a set of transistors with the same gate-length and gate-width that are processed in the same technology, will not yield the same results. During the fabrication process small variations will occur that result in a statistical variation of the transistor properties. This variation depends on the dimensions of the matched component and its biasing conditions. This phenomenon is referred to as transistor mismatch.

CMOS D/A Converter Architectures

In the previous chapter, the functionality of a D/A converter has been explained together with the specifications that describe its static and dynamic behaviour. This chapter discusses the different architectures for a D/A converter.

Dynamic Behaviour of Current Steering D/A Converters

As has been discussed in the previous chapter, the current steering topology is currently the preferred architecture for telecommunication applications requiring a high update rate and/or a high accuracy. Designing such a D/A converter requires a thorough understanding of both the static and the dynamic behaviour of this device.

The D/A Converter: Functionality and Specifications

Although the digital world is gaining in importance due to the decreasing feature size of transistors in the rapidly evolving semiconductor technology, the analog building blocks have proven to be indispensable. The advantages of digital processing (easier design, extensive programmability, ...) are counteracted by the fact that people perceive information in an analog form (f.i. speech). The design of the interface between the analog and the digital system (the A/D and the D/A converter) has to comply with the stringent specifications required by modern complex digital systems. Furthermore, additional problems -like the substrate noise coupling from the digital to the analog parts on the chip- add to the complexity of the design.

Systematic Design of High-Performance Data Converters

A systematic design methodology for high-speed high-accuracy D/A converters has been demonstrated. The methodology covers the complete design flow starting from the specification phase of the converter as macrocell in a larger system down to a fully synthesized and laid out implementation followed by a verification of the entire system with a behavioral model extracted from the actual designed converter. The well established performance-driven top-down design methodology is used to synthesize the D/A converter. Both commercially available and newly developed software tools (such as the Mondriaan layout tool for analog circuits with regular array-type layout patterns) support this methodology. The correctness and effectiveness of the methodology has been proven by the fabrication and measurement of three high-speed high-accuracy D/A converters. During the designs, the methodology was refined and supporting tools were developed, which finally resulted in a design productivity improvement by a factor of 2.75 x.