Geert Van der Plas

A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS

Wireless environments, high data rates and increased digitization require A/D converters with high dynamic range and large bandwidth at the lowest possible power consumption. A fully flexible continuous-time (CT) Δ Σ with programmable bandwidth, resolution and power consumption in 1.2 V 90 nm CMOS is presented able to satisfy those demands. By introducing flexibility into the core building blocks, a DR of 67/72/78/83 dB is achieved in maximum performance mode for WLAN, DVB, UMTS and BT for a power consumption of 6.8/5.5/6.4/5.0 mW, respectively. GSM operation is also feasible with a DR of 87 dB. For a given bandwidth, the flexibility allows to obtain the lowest power consumption for a desired performance. The overall energy efficiency is reached with a single-bit CT Δ Σ modulator avoiding high speed DEM circuits. Its low power consumption especially for high bandwidths is realized thanks to architecture and circuit level optimization. Linearity enhanced integrators, a threshold configurable comparator enabling loop delay compensation and optimized DAC implementations for jitter and avoiding signal dependency in the feedback pulses due to a large voltage swing are employed to increase the performance. The respective FOM equals 0.24/0.27/0.41/0.85 pJ per conversion.

Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ.

A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS

A 2.2 GS/s 4×-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. The folding stage samples the input, removes its common-mode component and rectifies the differential voltage. The pipelined binary-search sub-ADC leverages threshold calibration to correct for amplifier and comparator imperfections, which allows the use of inherently nonlinear dynamic amplifiers. The prototype achieves 31.6 dB SNDR at 2.2 GS/s with a 2 GHz ERBW for 2.6 mW power consumption in an area of 0.03 mm2.

A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS

Communication in the unlicensed frequency band around 60GHz requires a very fast ADC with low resolution. We present a four-way interleaved converter, of which one channel is shown in Fig. 16.3.1, for these requirements. Dynamic pipelined conversion enables low power quantization at high speed with low input capacitance but requires calibration. A folding front-end halves the required calibration effort.

Digital ground bounce reduction by phase modulation of the clock

The digital switching noise that propagates through the chip substrate to the analogue circuitry on the same chip is a major limitation for mixed-signal SoC integration. In synchronous digital systems, digital circuits switch simultaneously on the clock edge, hereby generating a large ground bounce. In order to reduce the spectral peaks in the ground bounce spectrum, we combine the two techniques: (1) phase modulation of the clock; and (2) introducing intended clock skews to spread the switching activities. Experimental results show around 16 dB reductions in the spectral peaks of the noise spectrum when these two techniques are combined. These two techniques are believed to be good candidates for the development of methodologies for digital low-noise design techniques in future CMOS technologies.

Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design

In this paper we present test structures and measurement techniques that enable extraction of significance of effects expected in 3D TSV technologies. The DAC test structure is optimized to detect Ion changes down to 0.5 % due to TSV proximity, TSV orientation, thermal hotspots and wafer thinning/stacking process. The results obtained from the stand-alone MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors.

DRAM-on-logic Stack – Calibrated thermal and mechanical models integrated into PathFinding flow

In this paper, we present thermal and mechanical characterization of a DRAM-on-logic stack. Our experimental data indicates that a holistic optimization of design and technology is needed to achieve working 3D stacks. Particularly, the stack organization and TSV/μbump layout must be fine-tuned together with the 3D technology for managing mechanical and thermal challenges. In order to support system designers, we propose hereto a dedicated thermal and mechanical model, integrated into the design flow. We also indicate the data required from foundries and OSATs to achieve good fidelity with measurement results.

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study

New technologies for manufacturing 3D Stacked ICs offer numerous opportunities for the design of complex and effcient embedded systems. But these technologies also introduce many design options at system/chip design level, hard to grasp during the complete design cycle. Because of the sequential nature of current design practices, designers are often forced to introduce design margins to meet required specications, resulting in sub-optimal designs. In this paper we introduce new design methodology and practical tool chain, called PathFinding Flow, that can help designers to easily trade-off between different system level design choices, physical design and/or technology options and understand their impact on typical design parameters such as cost, performance and power. Proposed methodology and the tool chain will be demonstrated on a practical case study, involving fairly complex Multi-Processor System-on-Chip using Network-on-Chip for communication medium. With this example we will show how High-Level Synthesis can be used to quickly move from high-level to RTL models, necessary for accurate physical prototyping for both computation and communication. We will also show how the possibility of design iteration, through the mechanism of feedback based on physical information from physical prototyping, can improve design performance. Finally, we will show how we can move in no time from traditional 2D to 3D design and how we can measure benets of such design choice.

Measurements and Analysis of Substrate Noise Coupling in TSV-Based 3-D Integrated Circuits

Silicon substrates can be strategically isolated or unified among tiers in a through-silicon-via (TSV)-based 3-D integrated circuit (IC) structure, for the suppression of intertier substrate noise coupling or the reduction of grounding impedance of silicon substrates as a whole, respectively. A two-tier 3-D IC demonstrator in a 130-nm CMOS technology was successfully tested and analyzed with respect to intra and intertier substrate noise coupling. Each tier in the stack includes digital noise source circuits (NSs) and substrate noise monitors, and embodies in-place measurements of substrate noise coupling. An equivalent circuit unifies power and substrate networks of the tiers and simulates the frequency-domain response of substrate noise coupling. Measurements and calculation with the equivalent circuit are consistent for frequency dependency of substrate noise coupling in a 3-D IC demonstrator. Intratier propagation is dominant, while intertier coupling is insignificant for low-frequency substrate noise components. Intertier coupling becomes comparable with and finally overwhelms intratier coupling as the frequency of substrate noise components increases. Substrate noise coupling in a multitier chip stack is strongly impacted by the parasitic capacitance of TSVs, while that coupling becomes predictable with the equivalent circuit of the entire stack.

Reliability concerns in copper TSV's: Methods and results

Due to their large volume and close proximity to devices, the reliability of copper TSVs is a concern, both with respect to mechanical stresses induced by the TSV in the Si and with respect to copper drift into the liner and the Si. This abstract summarizes recent achievements obtained in imecs 3D-reliability work package where above mentioned reliability concerns are evaluated in detail. To study the impact of mechanical stresses induced by the TSV in the Si, the saturation drain currents Id of transistors have been used as stress sensors. The offset of the Id of transistors closer to a TSV with respect to transistors far away from a TSV has been studied, both directly after processing and after thermal storage and thermal shock. It is shown that stresses generated by the TSV in the Si increase after thermal storage above certain temperatures while thermal shock reduces these stresses. The first is attributed to stress relaxation at high temperatures, while the latter is attributed to cracking/delamination at critical interfaces. To study continuity in TSV-barriers, a method, further referred to as dual ramp rate IVctrl, is introduced. The method consists of controlled current-voltage sweeps at different rates. The difference in breakdown fields for different ramp rates allows estimating TDDB (=Time Dependent Dielectric Breakdown) field acceleration parameters. Applying a negative voltage to the TSV (-V) does not allow copper to drift into the liner, while when applying a positive voltage (+V) to the TSV, copper can drift into the liner in case of a defective, non-continuous barrier. Comparing TDDB field acceleration parameters of -V versus +V tests gives insight in barrier properties. In our study, weak reliability is observed in systems where the TSV-barriers are not continuous.