J. Vandenbussche

A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC

In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q/sup 2/ random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-/spl mu/m CMOS process. The die area is 13.1 mm/sup 2/.

AMGIE-A synthesis environment for CMOS analog integrated circuits

A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the systems database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter

The design issues and tradeoffs of a high-speed high-accuracy Nyquist-rate analog-to-digital (A/D) converter are described. The presented design methodology covers the complete flow from specifications to verified layout and is supported by both commercial and internally developed computer-aided design tools. The major decisions to be made during the converters design at both the architectural and the circuit level are described and the tradeoffs are elaborated. The approach is demonstrated for a real-life test case, where a Nyquist-rate 8-bit 200-MS/s 4-2 interpolating/averaging A/D converter was developed in a 0.35-/spl mu/m CMOS technology. The signal-to-noise-plus-distortion ratio at 40 MHz is 42.7 dB and the total power consumption is 655 mW.

A 12 bit 200 MHz low glitch CMOS D/A converter

A 12-bit 200 MHz CMOS current steering D/A converter is presented. The measured glitch energy is 0.8 pVs. To obtain this very low glitch energy specification, a new driver circuit using a dynamic latch is proposed. The measured INL is better than +/-0.5 LSB. The D/A converter operates at a 2.7 V power supply, it has a 20 mA full swing output current and a 200 MHz conversion rate. The worst case power consumption is 140 mW at the maximum conversion rate. The chip has been processed in a standard 0.5 /spl mu/m CMOS technology.

A fully integrated low-power CMOS particle detector front-end for space applications

A fully integrated low-power complementary metal-oxide-semiconductor (CMOS) particle detector front-end (PDFE), optimized for space applications, is presented. The front-end comprises a charge sensitive amplifier and a four-stage semi-Gaussian pulse-shaping amplifier. The chip was custom synthesized with an analog synthesis environment. With a power consumption of only 10 mW and a chip area less than 1 mm/sup 2/, the chip is very well suited for the stringent demands in space applications. Measurements show a peaking time of 1.2 /spl mu/s and a total equivalent noise charge of less than 1000 e/sub rms//sup -/. Although a standard 0.7-/spl mu/m CMOS was used, little performance degradation was observed after exposure to a total dose irradiation of 50 kRad. All tested chips fully recovered within specifications, after 24 h of annealing at room temperature.

Behavioral model of reusable D/A converters

In the context of the Virtual Socket Interface (VSI) system on a chip interface for embedded blocks, a behavioral model of a digital-to-analog converter is presented. A generic model, which is used for high-level design exploration, as well as an extracted model after synthesis, are presented. Both static (integral nonlinearity, differential nonlinearity) and dynamic behavior (glitch behavior, settling time) are modeled accurately. Power and area estimators are derived as well. The model results in efficient system simulations.

EsteMate: a tool for automated power and area estimation in analog top-down design and synthesis

A novel methodology to derive power and area is presented. The method consists of the generation of a training set and a subsequent training of an Artificial Neural Network. The resulting estimators do not only predict power and area accurately and efficiently, they also reflect the complex interaction between different specifications. The method has been implemented in a tool, EsteMate, and is illustrated with practical examples.

Mondriaan: a tool for automated layout synthesis of array-type analog blocks

A tool set, Mondriaan, is proposed which targets the physical design automation of all array-type analog blocks. The approach takes in consideration typical analog constraints and is very flexible. A three step procedure (floorplan generation, symbolic place and route and technology mapping) solves the layout synthesis problem in a fast and technology independent way. Industrial strength examples show the applicability and usefulness of the proposed solution.

A 12 b accuracy 300 Msample/s update rate CMOS DAC

Of several technology and architecture alternatives for >100 MHz >10 b DACs, CMOS current-steering DAC architectures are particularly suitable. (1) They can be designed in a standard digital CMOS technology, with evident cost and power consumption advantages in the integration with the digital circuits, and (2) They are intrinsically faster and more linear than competing architectures such as resistor-string DACs. This DAC is integrated in a standard digital 0.5 /spl mu/m CMOS technology. It has a current steering 6+2+4 segmented architecture: first, the six most significant bits (MSBs) are linearly decoded; second, the intermediate two bits are also linearly decoded, but independently from the MSBs; third, the four least significant bits are binary weighted.

Statistical behavioral modeling for A/D-converters

An automated method to derive the statistical parameters of the building blocks of A/D-converters is presented. This method is applied to an 8-bit full flash A/D-converter. The statistical model is used to simulate INL and DNL and explore statistical effects that cannot be captured in closed expressions. A speedup in simulation times of over 100 is reported compared to device-level simulations.