Anthony M. Phan

Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis

A comparison of two scrubbing mitigation schemes for Xilinx field programmable gate array devices is presented. The design of the scrubbers is briefly discussed along with an examination of mitigation limitations. Heavy ion data are then presented and analyzed.

Impact of Low-Energy Proton Induced Upsets on Test Methods and Rate Predictions

Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used to calibrate a Monte Carlo rate prediction model, which is used to evaluate the importance of this upset mechanism in typical space environments. For the ISS orbit and a geosynchronous (worst day) orbit, direct ionization from protons is a major contributor to the total error rate, but for a geosynchronous (solar min) orbit, the proton flux is too low to cause a significant number of events. The implications of these results for hardness assurance are discussed.

An Analysis of Single Event Upset Dependencies on High Frequency and Architectural Implementations within Actel RTAX-S Family Field Programmable Gate Arrays

In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz

32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches

Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.

Single-Event Effect Performance of a Commercial Embedded ReRAM

We show the single-event effect characteristics of a production-level embedded resistive memory. The resistive memory under investigation is a reduction-oxidation random access memory embedded inside a microcontroller. The memory structure consists of Ir top electrode, Ta2O5-δ/TaOx metal-oxide, and TaN bottom electrode. The radiation testing focused on the resistive memory array and peripheral circuits, while other portions of the microcontroller were shielded against the ion beam. We found that the resistive memory array is hardened against heavy ion and pulsed-laser-induced bit upsets. However, the microcontroller is susceptible to single-event functional interrupts due to single-event upsets in the resistive memory peripheral control circuits, which comprise of CMOS elements. Furthermore, the resistive memory architecture is not susceptible to functional failures during write, which is problematic for flash memories due to radiation-induced charge pump degradation.

Effects of Ion Atomic Number on Single-Event Gate Rupture (SEGR) Susceptibility of Power MOSFETs

The relative importance of heavy-ion interaction with the oxide, charge ionized in the epilayer, and charge ionized in the drain substrate, on the bias for SEGR failure in vertical power MOSFETs is experimentally investigated. The results indicate that both the charge ionized in the epilayer and the ion atomic number are important parameters of SEGR failure. Implications on SEGR hardness assurance are discussed.

Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

We report low-energy proton and low-energy alpha particle SEE data on a 32 nm SOI CMOS SRAM that demonstrates the criticality of using low-energy protons for SEE testing of highly-scaled technologies. Low-energy protons produced a significantly higher fraction of multi-bit upsets relative to single-bit upsets when compared to similar alpha particle data. This difference highlights the importance of performing hardness assurance testing with protons that include energy distribution components below 2 MeV. The importance of low-energy protons to system-level single-event performance is based on the technology under investigation as well as the target radiation environment.

The Effects of Elevated Temperature on Pulsed-Laser-Induced Single Event Transients in Analog Devices

We present results of laser-induced analog SETs at elevated temperatures. We found increasing pulse widths with increasing temperature for the LM124. We also observed increasing pulse amplitudes with increasing temperature for several sensitive transistors in the LM139. However the response from the input transistor was a rapidly shrinking SET, suggesting that the SET threshold increases at elevated temperatures for the input stage transistors. In addition we observed increases in the SET leading edge fall times with increasing temperature for the LM139 that are consistent with independently measured slew rates. Simulations revealed that the dominant mechanism is bipolar current gain enhancement at elevated temperatures. These temperature-induced changes to the SETs may have critical implications for radiation hardness assurance.

Current Single Event Effects Compendium of Candidate Spacecraft Electronics for NASA

We present the results of single event effects (SEE) testing and analysis investigating the effects of radiation on electronics. This paper is a summary of test results.

TPA Laser and Heavy-Ion SEE Testing: Complementary Techniques for SDRAM Single-Event Evaluation

We report on complementary use of two-photon absorption laser and heavy-ion SEE testing to evaluate the single-event response of SDRAMs. The tandem testing technique helps disentangle the response of devices exhibiting multiple SEE modes.