Melanie D. Berg

Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis

A comparison of two scrubbing mitigation schemes for Xilinx field programmable gate array devices is presented. The design of the scrubbers is briefly discussed along with an examination of mitigation limitations. Heavy ion data are then presented and analyzed.

Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM

Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events.

Low Energy Proton Single-Event-Upset Test Results on 65 nm SOI SRAM

Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed.

SEE and TID Characterization of an Advanced Commercial 2Gbit NAND Flash Nonvolatile Memory

An advanced commercial 2Gbit NAND flash memory (90 nm technology, one bit/cell) has been characterized for TID and heavy ion SEE. Results are qualitatively similar to previous flash results in most respects, but we also detected a new dynamic failure mode

Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST)

SEE testing at multi-Gbit/s data rates has traditionally involved elaborate high speed test equipment setups for at-speed testing. We demonstrate a generally applicable self test circuit approach implemented in IBMs 5AM SiGe process, and describe its ability to capture complex error signatures during circuit operation at data rates exceeding 5 Gbit/s. Comparisons of data acquired with FPGA control of the CREST ASIC versus conventional bit error rate test equipment validate the approach. In addition, we describe SEE characteristics of the IBM 5AM process implemented in five variations of the D flip-flop based serial register. Heavy ion SEE data acquired at angles follow the traditional RPP-based analysis approach in one case, but deviate by orders on magnitude in others, even though all circuits are implemented in the same 5AM SiGe HBT process.

Compendium of Current Single Event Effects Results for Candidate Spacecraft Electronics for NASA

Sensitivity of a variety of candidate spacecraft electronics to proton and heavy ion induced single event effects is presented. Devices tested include digital, linear, and hybrid devices.

An Analysis of Single Event Upset Dependencies on High Frequency and Architectural Implementations within Actel RTAX-S Family Field Programmable Gate Arrays

In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz

32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches

Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.

Electron-Induced Single-Event Upsets in Static Random Access Memory

We present experimental evidence of single-event upsets in 28 and 45 nm CMOS SRAMs produced by single energetic electrons. Upsets are observed within 10% of nominal supply voltage for devices built in the 28 nm technology node. Simulation results provide supporting evidence that upsets are produced by energetic electrons generated by incident X-rays. The observed errors are shown not to be the result of “weak bits” or photocurrents resulting from the collective energy deposition from X-rays. Experimental results are consistent with the bias sensitivity of critical charge for direct ionization effects caused by low-energy protons and muons in these technologies. Monte Carlo simulations show that the contributions of electron-induced SEU to error rates in the GEO environment depend exponentially on critical charge.

TID and SEE Response of Advanced Samsung and Micron 4G NAND Flash Memories for the NASA MMS Mission

SEE and TID results are presented for two advanced commercial flash memories, Samsung and Micron 4 Gb. Both have very good TID response, and very good SEU bit error rates, but the Samsung parts have lower SEFI rates and lower rates of destructive failures.