Antonios Bazigos

Room-Temperature Negative Differential Resistance in Graphene Field Effect Transistors: Experiments and Theory

In this paper we demonstrate experimentally and discuss the negative differential resistance (NDR) in dual-gated graphene field effect transistors (GFETs) at room temperature for various channel lengths, ranging from 200 nm to 5 μm. The GFETs were fabricated using chemically vapor-deposited graphene with a top gate oxide down to 2.5 nm of equivalent oxide thickness (EOT). We originally explain and demonstrate with systematic simulations that the onset of NDR occurs in the unipolar region itself and that the main mechanism behind NDR is associated with the competition between the specific field dependence of carrier density and the drift velocity in GFET. Finally, we show experimentally that NDR behavior can still be obtained with devices of higher EOTs; however, this comes at the cost of requiring higher bias values and achieving lower NDR level.

Investigation of tunnel field-effect transistors as a capacitor-less memory cell

In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented as double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) and with a total overlap of the back gate over the channel region (LG + LIN). A potential well is created by biasing the back gate (VBG) in accumulation, while the front gate (VFG) is in inversion. Holes from the p+ source are injected by the forward-biased p+ i junction and stored in the electrically induced potential well.

A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET

This paper presents a novel physics-based analytical compact model for the drift region of a high-voltage metal-oxide-semiconductor field-effect transistor (HV-MOSFET). According to this model, the drift region is considered as a simple 1-D problem, just as that of a low-voltage inner MOS transistor. It exploits the charge-sheet approximation and performs linearization between the charge in the drift region and the surface potential. The drift region model combined with the standard charge-sheet MOS model for the low-voltage part adds up to a complete HV-MOSFET model, which is verified against technology computer-aided design simulations and measurements of HV-MOS transistors. The comparisons demonstrate its accurate physics foundations and underline that this novel approach to the modeling of the drift region of the HV-MOSFET is promising.

Sensing with Advanced Computing Technology: Fin Field-Effect Transistors with High-k Gate Stack on Bulk Silicon

Field-effect transistors (FETs) form an established technology for sensing applications. However, recent advancements and use of high-performance multigate metal-oxide semiconductor FETs (double-gate, FinFET, trigate, gate-all-around) in computing technology, instead of bulk MOSFETs, raise new opportunities and questions about the most suitable device architectures for sensing integrated circuits. In this work, we propose pH and ion sensors exploiting FinFETs fabricated on bulk silicon by a fully CMOS compatible approach, as an alternative to the widely investigated silicon nanowires on silicon-on-insulator substrates. We also provide an analytical insight of the concept of sensitivity for the electronic integration of sensors. N-channel fully depleted FinFETs with critical dimensions on the order of 20 nm and HfO2 as a high-k gate insulator have been developed and characterized, showing excellent electrical properties, subthreshold swing, SS ∼ 70 mV/dec, and on-to-off current ratio, Ion/Ioff ∼ 10(6), at room temperature. The same FinFET architecture is validated as a highly sensitive, stable, and reproducible pH sensor. An intrinsic sensitivity close to the Nernst limit, S = 57 mV/pH, is achieved. The pH response in terms of output current reaches Sout = 60%. Long-term measurements have been performed over 4.5 days with a resulting drift in time δVth/δt = 0.10 mV/h. Finally, we show the capability to reproduce experimental data with an extended three-dimensional commercial finite element analysis simulator, in both dry and wet environments, which is useful for future advanced sensor design and optimization.

Steep slope VO 2 switches for wide-band (DC-40 GHz) reconfigurable electronics

This work proves the feasibility of electrically actuated, CMOS compatible, microwave VO₂ switches on SiO₂/Si substrates with low variability, 100% yield, better than 109 cycles lifetime, ultra-steep OFF-ON transition and better RF performance than previously reported VO₂ switches on Al₂O₃ substrates (flat -0.6 dB S_21-ON with -10 dB S_21-OFF at 40 GHz). The extensive characterization of the fabricated switches has led to an optimum design with maximized S_21-ON/S_21-OFF ratio and validation as a promising solution for wideband reconfigurable electronics.

Analytical Compact Model in Verilog-A for Electrostatically Actuated Ohmic Switches

Nowadays, electronics face a challenge regarding the power consumption of integrated circuits (ICs). There is a need for new devices that can provide improved switching capabilities. The downscaled electrostatically actuated ohmic switch, as a (re)emerging device, is a promising candidate to meet this need. To bring such a device seamlessly into IC design, it must be accompanied by an accurate, fast and robust analytical compact model. The development and the main characteristics of such a model are described within this paper. Extensive numerical simulations and measurements have been used to validate the model.

Energy and Latency Optimization in NEM Relay-Based Digital Circuits

Digital circuits based on nanoelectromechanical (NEM) relays hold out the potential of providing an energy efficiency unachievable by conventional CMOS technology. This paper presents a detailed analysis of the operating characteristics of fabricated curved cantilever NEM relays using a comprehensive physical model. The mode of energy distribution within the electrical and mechanical operational domains of the relay is described in detail and the energy saving achievable by the technique of body-biasing is quantified. The analysis further reveals that the latency in a relay can be much larger or much smaller than the nominal mechanical delay depending on the point of actuation in the oscillation of the beam that takes place after pull-out. The methods that can utilize this phenomenon to reduce the latency of relay-based circuits are discussed, thus addressing one of the biggest challenges in NEM relay-based design.

Graphene Negative Differential Resistance Circuit With Voltage-Tunable High Performance at Room Temperature

We propose, fabricate, and experimentally demonstrate a circuit based on graphene field-effect transistors (GFETs) showing enhanced negative differential resistance (NDR) characteristics at room temperature. The proposed graphene NDR (GNDR) circuit consists of three GFETs, which includes a two GFET inverter connected in a feedback loop with the main GFET in which the NDR is realized. Herein, a GNDR circuit is demonstrated using large-area chemical vapor deposition grown graphene and no doping step, which makes it compatible with silicon-based circuits. The circuit shows negative differential conductance (2.1 mS/μm) that is almost an order of magnitude better than NDR based on 1-GFET. This conductance level is uniquely tunable (×2.3) with the supply voltage as well as with the back bias voltage. It also exhibits an improved peak-to-valley current ratio (2.2) and a wide voltage range (0.6 V) over which NDR is valid. In comparison with other NDR technologies, the GNDR has a very high peak-current-density of the order of 1 mA/μm , which offers unique opportunities for designing circuits for applications requiring high current drive.

Analysis of harmonic distortion in deep submicron CMOS

This paper presents a study of harmonic distortion measurement and modeling in an 0.14 um CMOS technology. Measurements and simulation of DC characteristics, as well as high-frequency harmonic distortion are presented. The new EKV3.0 compact MOSFET model is used to model DC and harmonic distortion characteristics.

A 6.7 MHz nanoelectromechanical ring oscillator using curved cantilever switches coated with amorphous carbon

Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low power digital electronics. This paper reports the demonstration of the first ring oscillator built using cell-level digital logic elements based on curved NEM switches. The NEM switch has a size of 5×3 μm2, an air gap of 60 nm and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator is a key milestone on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.