Aravind Tharayil Narayanan

High-

A helium-3 ion bombardment technique is proposed to realize high-

Q

Q

Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits

inductors by creating locally semi-insulating substrate areas. A dose of

A Fractional- N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

1.0\times 10^{13}

14.1 A 0.048mm 2 3mW synthesizable fractional-N PLL with a soft injection-locking technique

cm

High-Q inductors on locally semi-insulated Si substrate by helium-3 bombardment for RF CMOS integrated circuits

^{-2}

A pulse-driven LC-VCO with a figure-of-merit of −192dBc/Hz

helium-3 increases a Si substrate resistivity from 4

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection

\Omega \cdot

A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of −246dB

cm to above 1

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance

\text{k}\Omega \cdot