Bangan Liu

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay

It is predicted that the required wireless communication capacity will become 1000 times higher every 10 years. Many wireless standards are under discussion to satisfy the unprecedented capacity requirement. For example, the IEEE802.11ay standard is targeting over 100Gb/s data-rate by using the 60GHz band. Unfortunately, the channel bandwidth of 2.16GHz for the 60GHz band is not wide enough to realize such a high data-rate, so a channel-bonding capability is strongly demanded to extend the data-rate as well as 64-QAM support, achieving 42.24Gb/s. To realize 4-channel bonding operation with 64QAM, fine and wideband I/Q mismatch calibration is one of the remaining issues. In addition, an 8b 14.08GS/s ADC is required to support 42.24Gb/s, which is usually realized by a massive time-interleaved ADC, and needs unreasonably large power consumption. In this work, a frequency-interleaved (FI) architecture is employed for the 60GHz transceiver-side to mitigate the wideband I/Q mismatch issue and the ADC requirement. In addition, an asymmetric quadrature injection-locked oscillator (QILO) is proposed to widen the locking range.

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance

The 60GHz carrier with 9GHz bandwidth enables ultra-high-speed wireless communication in recent years [1–4]. To meet the demand from rapidly-increasing data traffic, the IEEE802.11ay standard is one of the most promising candidates aiming for 100Gb/s data-rate. Both higher-order digital modulation such as 128QAM and channel bonding at 60GHz are considered to be used in the IEEE802.11ay standard. However, the more severe requirements of LO feedthrough (LOFT) and image-rejection ratio (IMRR) have to be satisfied, so much higher accuracy in built-in calibration circuitry is required across the entire 9GHz spectrum for LOFT and I/Q imbalance calibration to achieve the required EVM.

An LC-DCO based synthesizable injection-locked PLL with an FoM of −250.3dB

This paper presents an LC-DCO based synthesizable injection-locked all-digital phase-locked loop. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm digital CMOS process, the chip occupies a core area of 0.12mm2. The measured integrated jitter is 0.142ps at a carrier of 3.0GHz while consuming a power of 4.6mW under 1V power supply. It achieves a figure of merit (FoM) of -250.3dB, which is the best for the synthesized PLL so far to the best knowledge of the authors.

A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI

A feedback current output digital to analog converter (DAC) is proposed to improve the linearity of frequency and reduce the power consumption in this synthesized PLL. All circuit blocks are implemented with standard cells from digital library and place-and-routed automatically without any manual routing. The proposed PLL has been fabricated in a 28 nm fully depleted silicon on insulator (FDSOI) technology. The measurement results show that this synthesized injection-locked PLL consumes 1.4mW from 1V supply while achieving a figure of merit (FoM) of −235.0 dB with 1.5 ps RMS jitter at 1.6GHz. This chip occupies only 64 μm × 64μm layout area with the advanced 28 nm FDSOI process. To the best knowledge of the authors, the PLL presented in this paper achieves the smallest area to date.

A 100mW 3.0 Gb/s spectrum efficient 60 GHz Bi-Phase OOK CMOS transceiver

A novel high-data-rate low-power spectrum-efficient 60GHz Bi-Phase-On-Off-Keying (BPOOK) transceiver is presented for indoor short-range IoT application targeting the common 60GHz spectrum mask used in IEEE 802.11ad/ WiGig standards. By employing bi-phase encoder and double-balanced mixer, the BPOOK transmitter spectrum is efficient to be compliant with 2-channel bonding spectrum mask. The proposed 60GHz OOK transceiver is fabricated in 65nm CMOS, achieves 3.0 Gb/s data-rate and −46 dBm sensitivity, while consuming a power of 100mW including the on-chip 60GHz synthesizer.

An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation

This paper presents an HDL-synthesized injection-locked phase-locked loop using LC-based DCO for on-chip clock generation. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm CMOS process, this prototype demonstrates a 0.142ps integrated jitter at 3.0GHz and consumes 4.6mW while only occupying an area of 0.12mm2. It achieves a figure of merit (FoM) of −250.3dB, which is the best for the synthesized PLL up-to-date.

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay

This paper presents 64-quadrature amplitude modulation (QAM) 60-GHz CMOS transceivers with four-channel bonding capability, which can be categorized into a one-stream transceiver and a two-stream frequency-interleaved (FI) transceiver. The transceivers are both fabricated in a standard 65-nm CMOS technology. For the proposed one-stream transceiver, the TX-to-RX error vector magnitude (EVM) is less than −23.9 dB for 64-QAM wireless communication in all four channels defined in the IEEE 802.11ad/WiGig. The maximum communication distance with the full rate can reach 0.13 m for 64 QAM, 0.8 m for 16 QAM, and 2.6 m for QPSK using 14-dBi horn antennas. A data rate of 28.16 Gb/s is achieved in 16 QAM by four-channel bonding. The transmitter, receiver, and phase-locked loop consume 186, 155, and 64 mW, respectively. The core area of the transceiver is 3.9 mm2. For the proposed two-stream FI transceiver, four-channel bonding in 64 QAM is realized with a data rate of 42.24 Gb/s and an EVM of less than −23 dB. The front end consumes 544 mW in transmitting mode and 432 mW in receiving mode from a 1.2-V supply. The core area of the transceiver is 7.2 mm2.