Kengo Nakata

13.3 A 56Gb/s W-band CMOS wireless transceiver

This paper presents a 56Gb/s 16-QAM 65nm CMOS transceiver using a W-band carrier. Two wideband IF signals are up- and downconverted simultaneously with 68GHz and 102GHz carriers. The transceiver achieves 56Gb/s data-rate with TX-to-RX EVM of -16.5dB within 0.1m distance. The transceiver consumes 260mW and 300mW from a 1V supply in TX and RX modes, respectively. This results in 10pJ/bit efficiency, which is a state-of-the-art-efficient high-data-rate mm-Wave CMOS transceiver.

A Fractional- N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This technique can be used for designing a fractional-N PLL with low in-band phase noise and low spurious tones with low power consumption. The short-current-free pipelined phase-interpolator used in this work is capable of achieving high-linearity with low-power while minimizing the intrinsic jitter. A number of other circuit techniques and layout techniques are also employed in this design for ensuring high-performance operation with minimal chip area and power consumption. The proposed fractional-N PLL is implemented in standard 65 nm CMOS technology. The PLL has an operating range of 600 MHz from 4.34 GHz to 4.94 GHz. In fractional-N mode, the proposed PLL achieves -249.5 dB FoM and less than -59 dBc fractional spurs.

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular

This paper presents a 27.5-29.6GHz fractional-N frequency synthesizer using reference and frequency doublers to achieve low in-band and out-of-band phase-noise for 5G mobile communications. The push-push amplifier and 28GHz balun help achieving differential signals with low out-of-band phase noise while consuming low power. A charge pump with gated offset as well as reference doubler help reducing noise-folding effect resulting low in-band phase noise while sampling loop filter helps reducing spurs. The proposed synthesizer has been implemented in 65nm CMOS technology achieving an in-band and out-of-band phase noise of -78dBc/Hz and -126dBc/Hz, respectively while consuming only 33mW. The jitter-power figure-of-merit (FoM) is -231dB which is the highest among the state-of-the-art >20GHz fractional-N PLLs. Reference spurs are less than -80 dBc.

14.1 A 0.048mm 2 3mW synthesizable fractional-N PLL with a soft injection-locking technique

Phase-locked loops (PLLs) are a crucial building block in modern Systems-on-Chip (SoCs), which contain microprocessors, I/O interfaces, memories, power management, and communication systems. Fully synthesizable PLLs [1-2], designed using a pure digital design flow, have been proposed to reduce the design cost and allow easier integration. To achieve high-frequency resolution, PLLs are required to operate in fractional-N mode, in addition to integer-N mode. There are several architectures available [5-6] for realizing fractional-N operation. However, the existing topologies are not well suited for synthesis, as they require a time-to-digital converter (TDC) [3] and a digital-to-time converter (DTC) [4-5]. TDCs and DTCs are vulnerable to layout uncertainty, arising from automatic place and route (P&R), introducing linearity degradation and leading to poor in-band and out-of-band phase noise in PLLs. Injection locking is a promising technique for synthesizable PLLs. Unfortunately, it suffers from large spur caused by a periodic hard refresh, and limited fractional resolution, which is bounded to the inverse of the number of ring oscillator delay stages [6]. This paper describes a fully synthesizable fractional-N PLL with a soft injection-locking technique for smoothing switching and fine fractional resolution, and a cascading topology for suppressing the free-running oscillator phase noise over a wide loop bandwidth.

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection

This paper presents an automatic place-and-routed two-stage fractional-N injection-locked PLL (IL-PLL) using soft injection technique for on-chip clock generation. Fabricated in a 65nm CMOS process, this prototype demonstrates a 3.6-ps integrated jitter at 1.5222 GHz and consumes 3mW leading to an FoM of -224.6 dB while only occupying an area of 0.048 mm2. It realizes the first fully synthesized fractional-N injection-locked PLL up-to-date.

A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of −246dB

This paper presents a fractional-N PLL working in sub-sampling mode using a pipelined phase-interpolator. The proposed pipelined phase-interpolator can achieve high phase linearity with very low power consumption. The fractional-N sub-sampling PLL is implemented in a standard 65nm CMOS technology. The PLL works at a frequency ranging from 4.3GHz to 4.9GHz while consuming 3.3mW. The measured in-band phase noise in fractional-N mode is -114dBc/Hz at 400kHz offset from the carrier, while working with a bandwidth of approximately 2MHz. The combination of high-precision low-power phase-interpolation technique and the sub-sampling technique realizes a high-performance fractional-N frequency synthesizer with the highest reported FoM.

8.5 A 0.42ps-jitter −241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO

This paper presents a supply regulated synthesizable injection-locked PLL (IL-PLL), using a noise-isolation LDO. The noise-isolation LDO realizes a time-shift operation to isolate the PLL from both supply and LDO noise, so the IL-PLL operation remains robust, even within a noisy SoC. The core layout of the PLL is implemented using solely a foundry provided standard-cell library for a 65nm CMOS process with standard digital design tools. Among synthesizable PLLs, jitter performance of 0.42ps is achieved with 3.8mW power consumption at 0.9GHz oscillation.

A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique

This paper proposes a noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. The phase interpolator helps reduce the jitter introduced into the system by the multi-phase generation mechanism used for the fractional operation. The proposed frequency synthesizer is fabricated in 65nm CMOS process and it is capable of working at frequencies ranging from 4.3GHz to 4.9GHz. The measured close-in phase noise is -113dBc/Hz at an offset of 200kHz from the carrier with 3.3mW power consumption, which results in a FoM of -246dB.