Hanli Liu

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad

This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance (-gm) of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves -78.5; dBc/Hz at 100 kHz offset, -122 dBc/Hz at 10 MHz offset, and a figure-of-merit (FoM) of -236 dB.

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular

This paper presents a 27.5-29.6GHz fractional-N frequency synthesizer using reference and frequency doublers to achieve low in-band and out-of-band phase-noise for 5G mobile communications. The push-push amplifier and 28GHz balun help achieving differential signals with low out-of-band phase noise while consuming low power. A charge pump with gated offset as well as reference doubler help reducing noise-folding effect resulting low in-band phase noise while sampling loop filter helps reducing spurs. The proposed synthesizer has been implemented in 65nm CMOS technology achieving an in-band and out-of-band phase noise of -78dBc/Hz and -126dBc/Hz, respectively while consuming only 33mW. The jitter-power figure-of-merit (FoM) is -231dB which is the highest among the state-of-the-art >20GHz fractional-N PLLs. Reference spurs are less than -80 dBc.

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance

The 60GHz carrier with 9GHz bandwidth enables ultra-high-speed wireless communication in recent years [1–4]. To meet the demand from rapidly-increasing data traffic, the IEEE802.11ay standard is one of the most promising candidates aiming for 100Gb/s data-rate. Both higher-order digital modulation such as 128QAM and channel bonding at 60GHz are considered to be used in the IEEE802.11ay standard. However, the more severe requirements of LO feedthrough (LOFT) and image-rejection ratio (IMRR) have to be satisfied, so much higher accuracy in built-in calibration circuitry is required across the entire 9GHz spectrum for LOFT and I/Q imbalance calibration to achieve the required EVM.

A 100mW 3.0 Gb/s spectrum efficient 60 GHz Bi-Phase OOK CMOS transceiver

A novel high-data-rate low-power spectrum-efficient 60GHz Bi-Phase-On-Off-Keying (BPOOK) transceiver is presented for indoor short-range IoT application targeting the common 60GHz spectrum mask used in IEEE 802.11ad/ WiGig standards. By employing bi-phase encoder and double-balanced mixer, the BPOOK transmitter spectrum is efficient to be compliant with 2-channel bonding spectrum mask. The proposed 60GHz OOK transceiver is fabricated in 65nm CMOS, achieves 3.0 Gb/s data-rate and −46 dBm sensitivity, while consuming a power of 100mW including the on-chip 60GHz synthesizer.