Mariusz Rawski

An application of functional decomposition in ROM-based FSM implementation in FPGA devices

Modern FPLD devices have very complex structure. They combine PLA like structures, as well as FPGA and even memory-based structures. However lack of appropriate synthesis methods do not allow fully exploiting the possibilities the modern FPLDs offer. The paper presents a general method for the synthesis targeted to implementation of sequential circuits using embedded memory blocks. The method is based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block. An appropriately chosen decomposition strategy may allow reducing the required memory size at the cost of additional logic cells for address modifier implementation. This makes possible implementation of FSMs that exceed available memory by using embedded memory blocks and additional programmable logic.

Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures

The functional decomposition of binary and multi-valued discrete functions and relations has been gaining more and more recognition. It has important applications in many fields of modern digital system engineering, such as combinational and sequential logic synthesis for VLSI systems, pattern analysis, knowledge discovery, machine learning, decision systems, data bases, data mining etc. However, its practical usefulness for very complex systems has been limited by the lack of an effective and efficient method for selecting the appropriate input supports for sub-systems. In this paper, a new effective and efficient functional decomposition method is proposed and discussed. This method is based on applying information relationship measures to input support selection. Using information relationship measures allows us to reduce the search space to a manageable size while retaining high-quality solutions in the reduced space. Experimental results demonstrate that the proposed method is able to construct optimal or near-optimal supports very efficiently, even for large systems. It is many times faster than the systematic support selection method, but delivers results of comparable quality.

Efficient Implementation of digital filters with use of advanced synthesis methods targeted FPGA architectures

This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, performance of multipliers implemented in FPGA architectures does not allow to constructs high performance digital filters. In this paper application of distributed arithmetic is demonstrated. Since in this approach combinational LUT blocks replace general purpose multipliers, it is possible to construct digital filters of very high performance. However LUT blocks can be of considerable size thus advanced synthesis methods have to be used to map them efficiently into FPGA resources. In this paper and application of the functional decomposition based synthesis has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures and allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.

The influence of the number of values in sub-functions on the effectiveness and efficiency of the functional decomposition

General functional decomposition has important applications in many fields of modern engineering and science. However, its practical usefulness for very complex systems is limited by the lack of an effective and efficient method for the construction of high quality sub-systems. One of the three basic problems of sub-system construction is the choice of an appropriate multi-valued sub-function to be computed by a certain sub-system. In this paper we show that the number of values of the sub-function is the decisive factor in sub-function selection. It shows a very strong positive correlation with both the number of logic blocks and the number of logic levels in the decomposition network, i.e. with the cost and delay of the network. This is a very important result from the practical viewpoint, because its exploitation enables efficient construction of high-quality multi-level circuits, by selection of a sub-function with the minimum possible number of values at each decomposition step. This result also gives a link for the input support selection for sub-systems. The selected input support should enable construction of a sub-function with the minimum possible number of values.

Non-disjoint decomposition of Boolean functions and its application in FPGA-oriented technology mapping

We present a new theory of non-disjoint serial decomposition. We also present our new decomposition tool DEMAIN. The decomposition approach implemented in DEMAIN relies on: a partition-based representation of Boolean functions; and an effective balanced decomposition strategy that switches between the parallel and non-disjoint serial decomposition. In consequence, we applied the non-disjoint serial decomposition and parallel decomposition for efficient synthesis of FPGA-based circuits directed towards area or delay optimisation.

5 Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks of FPGAs

The paper presents logic synthesis method targeted at FPGA architectures with specialized embedded memory blocks (EMBs). Existing methods do not ensure effective utilization of the possibilities provided by such modules. The problem of efficient mapping of combinational and sequential parts of design can be solved using decomposition algorithms. The main question of this paper is the application of decomposition based methods for efficient utilization of modern FPGAs. It will be shown that functional decomposition method allows for very flexible synthesis of the designed system onto heterogeneous structures of modern FPGAs composed of logic cells and EMBs. Finally we present results of the experiments, which evidently show, that the application of functional decomposition algorithms in the implementation of typical signal and information processing systems greatly influences the performance of resultant digital circuits.

FSM implementation in embedded memory blocks of programmable logic devices using functional decomposition

Since modern programmable devices contain embedded memory blocks, there exists the possibility of implementing finite state machines (FSM) using such blocks. However, the size of the memory available in programmable devices is limited. The paper presents a general method for the synthesis of sequential circuits using embedded memory blocks. The method is based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block. An appropriately chosen decomposition strategy may allow reducing the required memory size at the cost of additional logic cells for address modifier implementation. This makes possible the implementation of FSMs that exceed available memory by using embedded memory blocks and additional programmable logic.

Application of symbolic functional decomposition concept in FSM implementation targeting FPGA devices

This paper presents an FSM implementation method based on symbolic functional decomposition. This novel approach in multilevel logic synthesis of finite state machines targets FPGA architectures. Traditional methods are based on two steps: internal state encoding and then mapping the encoded state transition table into target architecture. In the case of FPGAs, functional decomposition is recognized as the most efficient method of implementing digital circuits. However none of the known state encoding algorithms can be considered as a good method to be used with functional decomposition. In this paper the concept of symbolic functional decomposition is applied to obtain a multilevel structure that is suitable for implementing in FPGA logic cells. The symbolic decomposition does not require separate encoding step. It accepts FSM description with symbolic states and performs decomposition introducing such a state encoding that guarantees the best solution known.

Efficient logic controller design

Logic controller is a digital device used for automation of electromechanical processes, such as control of machinery on factory assembly line or lighting fixtures. This paper presents the method for designing a logic controller. We implement it using reprogrammable structure equipped with Embedded Memory Blocks, e.g. CPLD or FPGA. We find that specification of the controller with appropriate statechart diagram and further synthesis as equivalent Finite State Machine yields encouraging results: the number of programmable resources has been reduced approximately by 85%. Result of the research is illustrated with synthesis of practical controllers, where hardware resource consumption is presented. It shows the usefulness of the approach.1

The Influence of Functional Decomposition on Modern Digital Design Process

General functional decomposition has been gaining more and more importance in recent years. Though it is mainly perceived as a method of logic synthesis for the implementation of Boolean functions into FPGA-based architectures, it has found applications in many other fields of modern engineering and science. In this paper, an application of balanced functional decomposition in different tasks of modern digital designing is presented. The experimental results prove that functional decomposition as a method of synthesis can help implementing circuits in CPLD/FPGA architectures. It can also be efficiently used as a method for implementing FSMs in FPGAs with Embedded ROM Memory Blocks.