Arvind Sundarrajan

Optimized integrated copper gap-fill approaches for 2x flash devices

Physical vapor deposited (PVD) Cu seed layers have been successfully implemented for Cu gap-fill in feature sizes for the 2x nm flash devices. By tuning the incident angle of the incoming flux of Cu ions as well as utilizing the resputtering parameter, the overhang, sidewall coverage and asymmetry can be well controlled to enable complete fill by subsequent electrochemical deposition (ECD). Chemical vapor deposition (CVD) Cobalt (Co) films were also investigated as an enhancement layer for Cu gap-fill. It was observed that the insertion of a 1.5nm-thick CVD Co layer, deposited between a PVD Ta barrier and a Cu seed layer could effectively enhance gap-fill in the small geometry trench/via structures. The CVD Co enhancement layer could also significantly improve the electromigration (EM) resistance of the Cu interconnects. The Chemical Mechanical Polish (CMP) process was also developed to provide an integrated solution.

Metallization of sub-30 nm interconnects: Comparison of different liner/seed combinations

Narrow trenches with Critical Dimensions down to 17 nm were patterned in oxide using a sacrificial FIN approach and used to evaluate the scalability of TaN/Ta, RuTa, TaN + Co and MnOx metallization schemes. So far, the RuTa metallization scheme has proved to be the most promising candidate to achieve a successful metallization of 25 nm interconnects, providing high electrical yields and a good compatibility with the slurries used during CMP.

CPI Parametric Investigation of UBM-Al Interface for Cu Pillar Flip-Chip Application

Under bump metallization (UBM)-Al delamination is a high-value chip-package interaction reliability problem in flip-chip Cu pillar packaging. We devised a test vehicle for quick reliability assessment. We demonstrate that preclean is a critical step to ensure reliable UBM-Al adhesion and achieve bump shear strength >12 g/mil2 for 15-μm polymer opening. Key parameters affecting bump shear strength, such as UBM critical dimension (CD), polyimide (PI) CD, SiN CD, and PI thickness, were reviewed from both simulation and experimental standpoints and good agreement was achieved between the two. Based on the observed failure mode, a 1-D model was also proposed to correctly predict the experimental trend. Optimum design rules for Cu pillar were outlined. Chip-substrate assembly was demonstrated on 80-μm bump pitch with staggered bump configuration using mass reflow. Progressive thermal cycling was performed to evaluate package performance. Failure mode was found to be solder crack, verifying the improvement in UBM-Al adhesion.

Electrical parametric and reliability of 5×50um TSVs for 3D IC

We present electrical parametric and reliability of 5×50um through silicon vias (TSVs) for three dimensional integrated circuits (3D IC). Electrical parameters such as oxide breakdown voltage (V_bd^TSV), leakage current (I_leak^TSV), oxide capacitance (C_ox^TSV), dielectric constant (k), minimum capacitance (C_min^TSV), threshold voltage (V_th) and mobile oxide charges (Q_m) of blind TSVs are analyzed. And, the reliability of TSVs is analyzed with thermal cycling between -55°C to 125°C with a dwell time of 10-15 minutes by following JEDEC standard No. 22-A104D.

Fabrication and electrical characterization of 5×50um through silicon vias for 3D integration

We present fabrication, electrical characterization, and metrology analysis results of 5×50um TSVs for 3D integration. Specifically, electrical performance of blind TSVs is evaluated by capacitance-voltage (CV) and current-voltage (IV) measurements. Important electrical parameters such as oxide capacitance, minimum TSV capacitance, leakage current, and breakdown voltage are extracted and show good results. The capacitance values also closely match model predictions. The electrical testing data are further verified with a variety of materials analysis techniques.

Modeling and Simulation of Physical Vapor Deposition/Etching Plasmas

A new physical vapor deposition source is developed to meet the challenges of barrier deposition for sub 100nm devices. The source employs multi-step process to deposit thin, conformal and uniform barrier films. This paper describes reactor scale modeling and simulation of deposition and etching plasmas used for barrier deposition. The modeling and simulation in tandem with experimental data demonstrate that the chamber can be used to independently control the particle fluxes as per the requirements of the deposition and etching steps. The simulation results were qualitatively used to optimize the ion flux uniformity by altering the magnetic fields near the wafer.© 2005 ASME