Murali Narasimhan

Correlation between aluminum alloy sputtering target metallurgical characteristics, arc initiation, and in-film defect intensity

Increasing levels of metallization, shrinking device geometries, and stringent defect density requirements have led to a continuous focus in the semiconductor manufacturing community to reduce defects generated during metal deposition by PVD techniques. Of particular interest in the metallization community is the reduction in in-film defect density in sputtered aluminum films. Pareto analysis of in-film defects in currently used interconnect metallization schemes suggest that a considerable portion of the in-film defects (up to 50%) are caused by unipolar arcing during aluminum deposition. Due to their unusual molten appearance, these defects are commonly referred to as splats. These defects can be as large as 500 micrometers , and due to their frequency of occurrence and size can significantly impact device yield in a manufacturing environment. Systematic investigations have revealed that the formation of splats, due to unipolar arcing, can be strongly correlated to the metallurgy of the aluminum alloy targets used during aluminum sputter deposition. The presence of undesirable metallurgical attributes such as alumina inclusions, porosity, oxygen content etc. are the primary causes for the occurrence of unipolar arcing. These undesirable metallurgical attributes appear to be the result of the manufacturing processes used to manufacture the aluminum alloy targets. The results of this study indicate that significant improvement in defect generation due to unipolar arcing during sputter deposition of aluminum films, and hence an improvement in device yield, is possible by reduction/elimination of the various undesirable metallurgical attributes in the aluminum alloy targets.

Optimized integrated copper gap-fill approaches for 2x flash devices

Physical vapor deposited (PVD) Cu seed layers have been successfully implemented for Cu gap-fill in feature sizes for the 2x nm flash devices. By tuning the incident angle of the incoming flux of Cu ions as well as utilizing the resputtering parameter, the overhang, sidewall coverage and asymmetry can be well controlled to enable complete fill by subsequent electrochemical deposition (ECD). Chemical vapor deposition (CVD) Cobalt (Co) films were also investigated as an enhancement layer for Cu gap-fill. It was observed that the insertion of a 1.5nm-thick CVD Co layer, deposited between a PVD Ta barrier and a Cu seed layer could effectively enhance gap-fill in the small geometry trench/via structures. The CVD Co enhancement layer could also significantly improve the electromigration (EM) resistance of the Cu interconnects. The Chemical Mechanical Polish (CMP) process was also developed to provide an integrated solution.

Study of wetting properties of Ti/TiN liners deposited by ion metal plasma PVD for low-temperature sub-0.25-um Al fill technology

Ti/TiN liners deposited with Vectra IMPTM (Ion Metal Plasma) PVD technology can be used as wetting layers to lower the temperature of Al planarization. The Ti/TiN liners can also be used to improve the texture and morphology of the Al overlayer. An experimental investigation was performed to study the impact of the IMP PVD process on the wetting properties of the Ti/TiN films. The Ti/TiN underlayers and the Al overlayer were studied for film morphology and texturing using AFM, XRD, and TEM techniques. It was found that the IMP Ti/TiN process can be used to control and optimize the fill capabilities of low temperature Al planarization. Parameters such as process pressure, bias, process temperature of the IMP Ti and TiN process as well as the wetting layer thickness have significant effects on the grain size, reflectivity, crystal orientation, and surface roughness of the aluminum films. Al films with high reflectivity, low roughness and hyper texturing (< 1 degree(s) FWHM) have been obtained with the integration of IMP Ti/TiN liner module with a low temperature Al planarization module. The fill capability of this integrated process exceeds that of the conventional high temperature Al planarization process at the Via level for a sub 0.25 micrometers IC process.

Metallization of sub-30 nm interconnects: Comparison of different liner/seed combinations

Narrow trenches with Critical Dimensions down to 17 nm were patterned in oxide using a sacrificial FIN approach and used to evaluate the scalability of TaN/Ta, RuTa, TaN + Co and MnOx metallization schemes. So far, the RuTa metallization scheme has proved to be the most promising candidate to achieve a successful metallization of 25 nm interconnects, providing high electrical yields and a good compatibility with the slurries used during CMP.

Ultrathin integrated ion metal plasma titanium and metallorganic titanium nitride liners for sub 0.18 μm W based metallization schemes for >500 MHz microprocessors

This study will specifically address the results of integrating IMP Ti and MOCVD TiN on a high vacuum system. Results of design of experiments used for process characterization and optimizing device parametric such as contact and via resistance will be discussed, in particular with respect to unlanded via schemes. Finally, Cost of Ownership calculations will be presented in comparison to conventional PVD technologies. In summary, the integration of IMP Ti and MOCVD TiN enables the deposition of a highly cost effective, low resistivity, ultra-thin, and low- temperature liners for sub 0.18 micrometers technology node thereby enabling > 500 MHz microprocessor technology.

Integrated arc suppression unit for defect reduction in PVD applications

Arcing between the target and plasma during PVD deposition causes substantial damage to the target and splats and other contamination on the deposited films. Arc-related damages and defects are frequently encountered in microelectronics manufacturing and contributes largely to reduced wafer yields. Arcing is caused largely by the charge buildup at the contaminated sites on the target surface that contains either nonconducting inclusions or nodules. Arc suppression is a key issue for defect reduction, yield improvement and for reliable high quality metallization. An Integrated Arc Suppression Unit (IASU) has been designed for Endura HP PVDTM sputtering sources. The integrated design reduces cable length from unit to source and reduces electrical energy stored in the cable. Active arc handling mode, proactive arc prevention mode, and passive by-pass arc counting mode are incorporated into the same unit. The active mode is designed to quickly respond to chamber conditions, like a large chamber voltage drop, that signals a arc. The self run mode is designed to proactively prevent arc formation by pulsing and reversing target voltage at 50 kHz. The design of the IASU, also called mini small package arc repression circuit--low energy unit (mini Sparc-le), has been optimized for various DC magnetron sources, plasma stability, chamber impedance, power matching, CE MARK test, and power dissipation. Process characterization with Ti, TiN and Al sputtering indicates that the unit has little adverse impact on film properties. Mini Sparc-le unit has been shown here to significantly reduce splats occurrence in Al sputtering. Marathon test of the unit with Ti/TiN test demonstrated the units reliability and its ability to reduce sensitivity of defects to target characteristics.

Statistical design of experimental analysis of TiN films deposited by ion metal plasma PVD for sub-0.25-um IC process applications

A Vectra IMPTM (Ion Metal Plasma) source was used to deposit TiN films for application such as W plug liner and Al wetting layer. The process is based on conventional magnetron sputtering with the addition of a higher density, inductively coupled RF plasma between the sputtering cathode and the substrate. This new technology enables deposition of the films into deep submicron contacts with >50% bottom coverage. In addition to enhancing step coverage of metal films, such as Ti and TiN, this process also has significant effects on the materials properties of the films. The film properties of the TiN films were studied as a function of the fundamental process parameters, namely DC target power, RF coil power, and chamber process pressure, using statistical DOE technique. The study shows that a high degree of control over the film properties can be obtained in the IMP process.

Characterization of PECVD Ti process and development of a plasma-less chlorine clean for process repeatability in advanced DRAM manufacturing

The TiCl4 based CVD-Ti process has been identified as the candidate of choice for the advanced contact metallization. A BKM wet clean recovery (WCR) procedure, involving extended chamber seasoning, has been developed for the CVD-Ti process. The new WCR methodology takes only 5 wafer processing to stabilize the CVD-Ti chamber condition and film properties. It has been found that a chamber seasoning for 200 sec, performed after every idle time (greater than 15 min.) and thermal periodic clean (at wafer count # 200), helps to maintain the CVD-Ti process performance. The reliability of the new chamber operating procedures was validated through a successful 3000 wafer marathon demonstration.

Enabling and cost-effective TiCl4-based PECVD Ti and CVD TiN processes for gigabit DRAM technology

This paper discusses TiCl4 based PECVD Ti and CVD TiN processes that enable a critical contact technology for cost effective gradient DRAMs. The PECVD Ti contact silicidation process and the CVD TiN barrier process together allow for reliable contact metallization with excellent contact resistance and leakage current performance for aspect ratios >12:1. Such capability has allowed a substantial increase in capacitor height alleviating the need for either a change in the capacitor dielectric as well as allowing the continuation of the bitline over capacitor metallization architecture. In addition, the in-situ silicidation capability of the PECVD Ti process allows for the elimination of the contact silicidation anneal step. When used as the top electrode in Ta2O3 based capacitor structures, TiCl4 based CVD TiN provides for reliable metallization with excellent leakage current performance. Preliminary results show that CVD TiN provides the capability for a complete plug fill with no peeling or cracking.

Capping layers, cleaning method, and rapid thermal processing temperature on cobalt silicide formation

The effect of some key variables such as rapid thermal processing (RTP) temperature, substrate cleaning method and capping layers, on cobalt silicide formation has been investigated. The in-situ RF sputter etch is found to give a post RTP2 Rsh that is equivalent to a wet cleaned wafer. The temperature transformation curve of cobalt films, analyzed with Rsh data and XRD, reveal the formation of Co2Si-CoSi-CoSi2 phases in that order. The transformation curves of TiN capped films match those of blanket cobalt but the Ti capped films show the CoSi phase to be stable over a broader temperature range. There is no effect of dopants on the final cobalt disilicide Rsh values for either the single of polycrystalline substrates. Controlled oxygen leak studies in the RTP ambient reveal that the Rsh after RTP1 is degraded if a capping layer is not present. Electrical test results confirm the need for capping layers. This is indicated by lower Rsh and Rc values on both n+ and p+ junctions and poly structures. Furthermore the electrical results are comparable for Ti and TiN layers used as the cap films although the Rsh/Rc values are in general lower for the TiN capped films. Poly gate length vs Rsh plots show the extendibility of the capped cobalt silicide process to the 0.18 um node.