Jungwoo Joh

Total current collapse in high-voltage GaN MIS-HEMTs induced by Zener trapping

We investigate current collapse in GaN MIS-HEMTs for >600 V operation. Extreme trapping leading to total current collapse has been observed after OFF-state stress at high voltage. We attribute this to high-field tunneling-induced electron trapping (“Zener trapping”) inside the AlGaN barrier or the GaN channel layers. The trapping takes place in a narrow region right under the edge of the outermost field plate in the drain portion of the device. The trapping characteristics are consistent with those responsible for the yellow luminescence band in GaN or AlGaN. This finding gives urgency to defect control during epitaxial-growth and the design of appropriate field plate structures for the reliable high-voltage operation of MIS-HEMTs.

Current collapse in GaN heterojunction field effect transistors for high-voltage switching applications

We have investigated current collapse in GaN heterojunction field effect transistors (HFETs) for high voltage power switching applications. With a novel technique in which the gate and drain pulses are controlled independently, we have measured the current collapse under various switching conditions. We found that the current collapse improves under hard switching in which the loadline passes through high current and high voltage area. This was attributed to holes that are generated through impact ionization and compensate trapped electrons at device surface. We show that optimized field plate and surface treatment significantly improves the current collapse for high voltage GaN HFETs.

Time-Dependent Dielectric Breakdown in High-Voltage GaN MIS-HEMTs: The Role of Temperature

We have investigated time-dependent dielectric breakdown in high-voltage AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistors, with a focus specifically on the role of temperature under positive gate stress conditions. We aim toward understanding the temperature dependence of progressive breakdown (PBD) as well as hard breakdown. We find that the temperature dependence of time-to-first breakdown, hard breakdown, and the gate current evolution during PBD all share similar, shallow activation energies that suggest a common underlying mechanism. However, the gate current noise during PBD seems to be independent of temperature and is likely due to a tunneling process. Understanding of temperature-dependent breakdown is essential to developing accurate device lifetime estimates.

Application reliability validation of GaN power devices

Standard qualification methodology or “qual” does not specify product-level testing due to the diverse range of products and use conditions, a limited ability for system-level acceleration, and complication from system-level failures. This is a concern for emerging power-management technologies, since the fundamental switching transitions are not covered. We show that hard-switching with the well-known double-pulse tester is predictive of device performance under system-level testing. It simplifies the problem of product reliability testing to one of a device and a tester. It enables us to detect devices that pass qual but perform poorly in application. As a result, our devices pass qual and perform well in application.

Electromigration in strapped metal layers with large dimensions for lateral power device applications

Interconnects for lateral power devices generally have multiple metal layers that are wide and thick to carry large current. Often times, these metal layers are also strapped together. In order to investigate the electromigration (EM) reliability for such metal systems, we stress an interconnect that straps three metal layers (ohmic contact metal (M0), M1, and M2) at 500 mA, 225°C; 400 mA, 225°C; and 500 mA 210°C. It shows three distinctive failure modes of early and late failures, and immortality. Massive voiding at M1 takes place with overhang effect, and voiding at M2 step turns out as the fatal failure mode. The temperature gradient over the M2 step is simulated and identified as a root cause of this failure. For the late fails, metal layer thickening and PO layer lift-up are newly observed, which are attributed to the massive force from the thickening of large dimensional M1 layer. These results provide new insights on the EM reliability of lateral power devices, contrasting to the Cu (or Al) voiding failure completely confined in the interconnect for CMOS circuits.