Ashima B. Chakravarti

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described in this paper. Gate length and dielectric scaling, along with optimized strain engineering, enable high performance devices, which are amongst the best reported to date. Short channel effect control down to 35 nm is demonstrated. Both NMOS and PMOS performance are improved through careful optimization of stress effects from both trench isolation and contact etch stop nitride film. Furthermore, analysis of the channel mobility and current enhancement is used to gain understanding of the stress mechanisms, and hence layout design practice should be optimized for performance.

Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy

Current drive enhancement is demonstrated in sub-40 nm NFETs with strained silicon carbon (Si:C) source and drain using a novel solid-phase epitaxy (SPE) technique for the first time. The very simple process uses no recess etch or epi deposition steps, adds minimal process cost, and can be easily integrated into a standard CMOS process. With a record high 1.65 at% substitutional C concentration in source and drain, 615 MPa uniaxial tensile stress was introduced in the channel, leading to a 35% improvement in electron mobility and 6% and 15% current drive increase in sub-40 and 200 nm channel length devices respectively.

Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow

Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN/sub x/) SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN/sub x/ for the NFET and ALD-WN/sub x/ for the PFET. Much enhanced drive current (I/sub d/) and transconductance (G/sub m/) values, and reduced off current (I/sub off/) characteristics were attained with ALD-MN/sub x/ gated devices over control poly-Si and PVD-MN/sub x/ devices within controllable V/sub t/ shifts. Excellent scalability of dual work function MN/sub x//high-k gate stack was demonstrated: the EOT was down to 6.6/spl Aring/ with low leakage in a low thermal budget device scheme.

Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

High quality ultra-thin TM-SGOI substrate with T/sub SOI/ < 55 nm is developed to combine the device benefits of strained silicon and SOI. 80-90% Id,sat and electron mobility increase are shown in long channel nFET device. For the first time, 20-25% device performance enhancement is demonstrated at 55 nm short channel strained silicon SGOI nFET devices.

High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor

For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45 nm-node nMOSFET with SMT and tensile liner stressors. In addition, eSi:C showed better scalability than SMT plus tensile liner stressors from 380 nm to 190 nm poly-pitches.

On implementation of embedded phosphorus-doped SiC stressors in SOI nMOSFETs

We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (Csub) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced Ieff and ~15% improved Idlin against the well calibrated control devices. It is found that the tensile liner technique provides further performance improvement for nFETs with SiC stressors, whereas the stress memory technique (SMT) does not provide performance gain in a laser annealing process that is used to preserve SiC strain. The material quality of the SiC stressors strongly affects strain transfer.

Recent Progress and Challenges in Enabling Embedded Si:C Technology

Summary In summary, this work demonstrates that integrating ISPD eSi:C stressor in the thick-oxide long-channel nMOS source and drain is feasible. Key challenges lie in both high-quality ISPD eSi:C EPI development and modification of the conventional Si CMOS fabrication process to preserve eSi:C strain. Acknowledgements This work was performed by IBM/AMD/Freescale Alliance Teams at various IBM Research and Development Facilities. We wish to thank Applied Materials and ASM America for supplying high quality eSi:C EPI materials. References: [1] Kah-Wee Ang, King-Jien Chui, Vladimir Bliznetsov, Yihua Wang, Lai-Yin Wong, Chih-Hang Tung, N. Balasubramanian, Ming-Fu Li, Ganesh Samudra, and Yee-Chia Yeo, IEDM Tech. Dig., p503, 2005.[2] Yaocheng Liu, Oleg Gluschenkov, Jinghong Li, Anita Madan, Ahmet Ozcan, Byeong Kim, Tom Dyer, Ashima Chakravarti, Kevin Chan, Christian Lavoie, Irene Popova, Teresa Pinto, Nivo Rovedo, Zhijiong Luo, Rainer Loesing, William Henson, Ken Rim, Symp. on VLSI Tech., p.44, 2007. [3] P. Grudowski, V. Dhandapani, S. Zollner, D. Goedeke, K. Loiko, D. Tekleab, V. Adams, G. Spencer, H. Desjardins, L. Prabhu, R. Garcia, M. Foisy, D. Theodore, M. Bauer, D. Weeks, S. Thomas, A. Thean, B. White, SOI Conf. Proc., p.17, 2007. [4] Zhibin Ren, G. Pei, J. Li, F. Yang, R. Takalkar, K. Chan, G. Xia, Z. Zhu, A. Madan, T. Pinto, T. Adam, J. Miller, A. Dube, L. Black, J. W. Weijtmans, B. Yang, E. Harley, A. Chakravarti, T. Kanarsky, I. Lauer, D.-G. Park, D. Sadana, and G. Shahidi, Symp. on VLSI Tech., P. 172-173, 2008. [5] A. Madan, J. Li, Z. Ren, F. Yang, E. Harley, T. Adam, R. Loesing, Z. Zhu, T. Pinto, A. Chakravarti, A. Dube, R. Takalkar, J. W. Weijtmans, L. Black, D. Schepis, ECS SiGe and Realted Materials and Devices Symposium, Hawaii, Oct. 2008 (to be published).

Characterization of bis(tertiary-butylamino)silane-based low-pressure chemical vapor deposition silicate glass films

The bis(tertiary-butylamino)silane-based low-pressure chemical vapor deposition (LPCVD) undoped silicate glass and phospho-silicate glass (PSG) processes were investigated to study film composition, etch rate, and step coverage. Through the addition of phosphorous doping, LPCVD PSG processing offers an attractive low temperature option. Enhanced deposition rate for the PSG process enables the lowering of the deposition temperature to the 400–500 °C range, thereby minimizing the thermal cycle and offering compatibility with many back-end-of-line processes. Many properties of these films are similar to those of the tetraethoxysilane (TEOS)-based LPCVD oxide. Differences in the film properties compared with the TEOS-based LPCVD oxide films can be traced to the composition of these films and the reaction mechanism.

Effect of Ion Implantation and Anneals on Fully-strained SiC and SiC:P Films using Multiple Characterization Techniques

In addition to device scaling, strain engineering using SiC stressors in the S/D regions is important for nFET performance enhancement [1-3]. In this paper, we review the characterization of fully-strained epitaxial SiC and in-situ doped SiC:P films for various ion implant conditions and anneals that are typically used in traditional CMOS flows. μXRD strain measurements and SIMS (C and P content) were performed on reference test macros on patterned lithographic wafers. μXRD strain measurements (related to substitutional C) of the asdeposited SiC films show that the C is lower than the actual C suggesting that there is interstitial C in the film. After M1 device measurements, Nanobeam Diffraction (NBD) analysis to determine channel strain was done on selected samples. An in-line μXRD system was used to monitor the strain and thickness variation of the SiC stressor with critical processing steps. Typical uXRD measurements demonstrate that there is a depth profile for the crystalline integrity of the SiC stressor films. The top surface which is in the implant range shows no strain (amorphization due to implants) compared to the fully strained, deeper regions (Fig 1). Figure 2 shows a typical cross-sectional TEM image and NBD patterns with the as-deposited SiC embedded in the source and drain. After M1 device measurements, good correlation was seen between the NBD and uXRD measurements (Fig 3). Stressor strain for samples 1-4 was retained after complete processing. Sample 5 which saw a high temperature anneal showed a complete loss of strain. This correlated well with the device results [4]. Full characterization has helped identify process integration schemes which give significant drive current enhancements [4].