Ashok Raman

Nonuniform total-dose-induced charge distribution in shallow-trench isolation oxides

A new approach for modeling the radiation-induced charge distribution in shallow-trench isolation (STI) structures shows that much less charge is trapped near the top of the trench. We found that charges inside the STI oxide are pushed down by the vertical electric field coming from the positive gate bias, leaving much less total-dose-induced charge close to the top of trench. This nonuniformity significantly affects the measured leakage current.

Fast, automated thermal simulation of three-dimensional integrated circuits

Three-dimensional (3D) stacked integrated circuits (ICs) can significantly improve circuit performance and offer the promise of integrating various technologies (memory, logic, RF, mixed-signal, optoelectronics) within a single block. Lack of 3D design tools and heat dissipation from vertically stacked multiple layers are the crucial problems in their development. To address these issues, CFD Research Corporation (CFDRC) is developing methodologies and tools to analyze and assess coupled electrical and thermal performance of 3D ICs, including calculation of realistic full-chip thermal distributions and determining from them signal delay/distortion. Due to the stacking technology, extensive localized heating can occur. Analysis to minimize these hot spots using thermal vias is demonstrated. Our Python-script based framework allows to drive and control all the aspects of the 3D model building (directly from layouts), thermal simulations, and results extraction/post-processing. Hence, it is a good basis for coupling with Electronic Design Automation (EDA) systems. We present results of automated, fast, but detailed thermal simulations of 3D stacked integrated circuits. In addition, procedures for automatic extraction of reduced and compact thermal-resistance-based 3D models have been implemented. These techniques greatly reduce required computational time, and allow for very fast parametric modeling analysis of 3D IC design configurations and temperature extraction. From these thermal resistance models, equivalent SPICE netlists may be generated and used for independent or coupled thermal analysis.

An Evaluation of Transistor-Layout RHBD Techniques for SEE Mitigation in SiGe HBTs

We investigate transistor-level layout-based techniques for SEE mitigation in advanced SiGe HBTs. The approach is based on the inclusion of an alternate reverse-biased pn junction (n-ring) designed to shunt electron charge away from the sub-collector to substrate junction. The inclusion of the n-ring affects neither the DC nor AC performance of the SiGe HBT and does not compromise its inherent multi-Mrad TID tolerance. The effects of ion strike location and angle of incidence, as well as n-ring placement, area, and bias on charge collection are investigated experimentally using a 36 MeV O2 microbeam. The results indicate that charge shunting through the n-ring can result in up to a 90% reduction in collector collected charge for strikes outside the DT and a 18% reduction for strikes to the emitter center. 3-D transient strike simulations using NanoTCAD are used to verify the experimental observations, as well as shed insight into the underlying physical mechanisms. Circuit implications for this RHBD technique are discussed and recommendations made.

Reconciling 3-D Mixed-Mode Simulations and Measured Single-Event Transients in SiGe HBTs

Comprehensive 3-D mixed-mode simulations, including accurate modeling of parasitic elements present in the experimental setup, resulted in close agreement between simulated and experimentally-measured heavy-ion-induced transients in first-generation SiGe HBTs. We have identified the key factors affecting previous simulations and observed experimental differences. The approach employed is also applicable to other submicron, high-speed technologies. Furthermore, we present a plausible answer to the previously unexplained issue of higher collector currents in single-transistor SiGe HBT single-event transients under positive collector bias. The new observations and conclusions facilitate improved understanding and potential mitigation options.

An Investigation of Single-Event Effects and Potential SEU Mitigation Strategies in Fourth-Generation, 90 nm SiGe BiCMOS

The single-event effect sensitivity of fourth-generation, 90 nm SiGe HBTs is investigated. Inverse-mode, ≥1.0 Gbps SiGe digital logic using standard, unoptimized, fourth-generation SiGe HBTs is demonstrated and the inverse-mode shift register exhibited a reduction in bit-error cross section across all ion-strike LETs. Ion-strike simulations on dc calibrated, 3-D TCAD SiGe HBT models show a reduction in peak current transient magnitude and a reduction in overall transient duration for bulk SiGe HBTs operating in inverse mode. These improvements in device-level SETs are attributed to the electrical isolation of the physical emitter from the subcollector-substrate junction and the high doping in the SiGe HBT base and emitter, suggesting that SiGe BiCMOS technology scaling will drive further improvements in inverse-mode device and circuit-level SEE. Two-photon absorption experiments at NRL support the transient mechanisms described in the device-level TCAD simulations. Fully-coupled mixed-mode simulations predict large improvements in circuit-level SEU for inverse-mode SiGe HBTs in multi-Gbps, inverse-mode digital logic.

Accurate Modeling of Single-Event Transients in a SiGe Voltage Reference Circuit

Single-event transients (SETs) are modeled in a SiGe voltage reference using compact model and full 3-D mixed-mode TCAD simulations. The effect of bias dependence and circuit loading on device-level transients is examined with regard to the voltage reference circuit. The circuit SET simulation approaches are benchmarked against measured data to assess their effectiveness in accurate modeling of SET in SiGe analog circuits. The mechanisms driving the SET of this voltage reference are then identified for the first time and traced back to the original device transients. These results enable the differences between the simulation results to be explained, providing new insight into best practices for the modeling circuit SET in different circuit topologies and device technologies.

Addressing challenges in device-circuit modeling for extreme environments of space

The authors have implemented a robust CNSPACK-based linear equation solver in an in-house TCAD tool. This solver is enhanced with efficient matrix pre-conditioning algorithms to enable accurate handling of a wide scale of floating-point numbers. Sample results are shown for very low temperature radiation response of a 0.12-mum NMOSFET and I-V curves of 0.13-mum SiGe HBT. The solution is very stable. However, the match against corresponding experimental data is not good due to inaccuracy of physical models (ongoing work).

Simulating the Radiation Response of GaAs Solar Cells Using a Defect-Based TCAD Model

Three-dimensional TCAD simulations are used for physics-based prediction of space radiation effects in III-V solar cells, and compared with experimentally measured characteristics of a p+ n GaAs solar cell with AlGaAs window. Dark and illuminated I-V curves as well as corresponding performance parameters are computed and compared with experimental data for 2 MeV proton irradiation at various fluences. We analyze the role of majority and minority carrier traps in the solar cell performance degradation. The traps/defects parameters used in the simulations, for n-type and p-type GaAs, are derived from Deep Level Transient Spectroscopy (DLTS) data. The physics-based models allow a good match between simulation results and experimental data. However, assuming the device performance is dominated by a single recombination center is not adequate to completely capture the degradation mechanisms controlling the photovoltaic performance.

Layout Based Full Chip Thermal Simulations of Stacked 3D Integrated Circuits

This paper presents full-chip scale detailed thermal simulations of three-dimensional (3D) integrated circuit (IC) stacks. The inter-layer dielectric (ILD) and inter-metal dielectric (IMD) materials inside 3D IC stacks may cause extensive localized heating. The influence of multiple layers of dielectrics on heat trapping inside the 3D stack is analyzed. Different methods to minimize such localized heating are studied. It is shown that the use of thermal vias is very effective in heat dissipation from the hot spots. Comparisons are made between several 3D IC configurations to verify these conclusions.Copyright

Enabling mixed-mode analysis of nano-scale SiGe BiCMOS technologies in extreme environments

The latest enhancements to NanoTCAD mixed-mode software package, combining 3D physics-based nano-scale device models and unique mixed-mode interface to the Cadence Spectre circuit simulator, have enabled simulations and in-operation analysis of ionizing radiation single event effects (SEEs) in modern high-speed SiGe BiCMOS technologies and integrated circuits. Additionally, the NanoTCAD new, automated interface to Geant4 radiation models and the 3D solver capability to model very low temperature behavior, enable a comprehensive and accurate modeling of radiation effects in nano-scale systems, in the extreme radiation and temperature environments of space. Example simulations of SEEs affecting digital output of a 7.2GHz mixed-signal circuit are presented. Our mixed-mode modeling results compare very well with experimental data.