Kurt A. Moen

Predictive Physics-Based TCAD Modeling of the Mixed-Mode Degradation Mechanism in SiGe HBTs

We study mixed-mode stress degradation in SiGe HBTs using a novel physical TCAD model in which the processes of hot carrier generation within the semiconductor, carrier propagation to the oxide interface, and formation of interface traps are directly modeled. Transient degradation simulations using a calibrated 2-D SiGe HBT model correlate well with measured data. With this novel simulation tool, we investigate the bias dependence and location of interface traps and show that secondary holes produced by impact ionization are the dominant carrier to damage the emitter-base (EB) spacer oxide interface, confirming previously reported results. We also compare in detail trap formation at the EB spacer and shallow-trench-isolation (STI) oxide interfaces as a function of time and stress condition. At the STI oxide interfaces, we find that hot electrons and holes each dominate trap formation in different regions, and the hot carriers that reach the STI predominately originate outside of the selectively implanted collector, revealing the important role played by dopant diffusion from the extrinsic base of quasi-self-aligned SiGe HBTs.

Sub-1-K Operation of SiGe Transistors and Circuits

We present the first measurement results for silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and SiGe BiCMOS circuits operating in the sub-1-K regime. Robust transistor operation of a first-generation 0.5 times 2.5 times 4-mum2 SiGe transistor is demonstrated at package temperatures as low as 300 mK. In addition, a SiGe BiCMOS bandgap voltage reference is verified to be fully functional at operating temperatures below 700 mK. The SiGe voltage reference exhibits a temperature coefficient of 160 ppm/degC over the temperature range of 700 mK-300 K.

Total Dose and Transient Response of SiGe HBTs from a New 4th-Generation, 90 nm SiGe BiCMOS Technology

The total ionizing dose and laser-induced transient response of a new 4th generation 90 nm IBM SiGe 9HP technology are investigated. Total dose testing was performed with 63.3 MeV protons at the Crocker Nuclear Laboratory at the University of California, Davis. Transient testing was performed on the two-photon absorption system at Naval Research Laboratory. Results show that the SiGe HBTs are dose-tolerant up to 3 Mrad(SiO2) and exhibit reduced single event transients compared to earlier SiGe generations.

Reconciling 3-D Mixed-Mode Simulations and Measured Single-Event Transients in SiGe HBTs

Comprehensive 3-D mixed-mode simulations, including accurate modeling of parasitic elements present in the experimental setup, resulted in close agreement between simulated and experimentally-measured heavy-ion-induced transients in first-generation SiGe HBTs. We have identified the key factors affecting previous simulations and observed experimental differences. The approach employed is also applicable to other submicron, high-speed technologies. Furthermore, we present a plausible answer to the previously unexplained issue of higher collector currents in single-transistor SiGe HBT single-event transients under positive collector bias. The new observations and conclusions facilitate improved understanding and potential mitigation options.

Single-Event Response of the SiGe HBT Operating in Inverse-Mode

The single-event effect sensitivity of inverse-mode biased SiGe HBTs in both bulk and SOI technology platforms are investigated, for the first time, using digital circuits and stand-alone device test structures. Comparisons of heavy-ion broad beam data of shift register circuits constructed with forward-mode and inverse-mode biased SiGe HBTs from a first-generation, complementary SOI SiGe BiCMOS process, reveal an improvement in SEU mitigation for the inverse-mode shift register architecture. Full 3D TCAD simulations highlight the differences in transient current origination between forward and inverse-mode biased devices, illustrating the impact of doping profiles on ion-induced shunt duration. To extend the analysis to a bulk platform, new fourth-generation npn , SiGe HBTs were biased in both the forward and inverse-mode and irradiated at NRL using the two photon absorption measurement system. These measurements support the analysis of transient origination using 3D TCAD simulations. Furthermore, the isolation of the output terminal from the sensitive subcollector-substrate junction is experimentally demonstrated for the inverse-mode bias. Fully coupled mixed-mode simulations predict a significant reduction in sensitive area for inverse-mode shift registers built in a bulk SiGe platform.

An Investigation of Single-Event Effects and Potential SEU Mitigation Strategies in Fourth-Generation, 90 nm SiGe BiCMOS

The single-event effect sensitivity of fourth-generation, 90 nm SiGe HBTs is investigated. Inverse-mode, ≥1.0 Gbps SiGe digital logic using standard, unoptimized, fourth-generation SiGe HBTs is demonstrated and the inverse-mode shift register exhibited a reduction in bit-error cross section across all ion-strike LETs. Ion-strike simulations on dc calibrated, 3-D TCAD SiGe HBT models show a reduction in peak current transient magnitude and a reduction in overall transient duration for bulk SiGe HBTs operating in inverse mode. These improvements in device-level SETs are attributed to the electrical isolation of the physical emitter from the subcollector-substrate junction and the high doping in the SiGe HBT base and emitter, suggesting that SiGe BiCMOS technology scaling will drive further improvements in inverse-mode device and circuit-level SEE. Two-photon absorption experiments at NRL support the transient mechanisms described in the device-level TCAD simulations. Fully-coupled mixed-mode simulations predict large improvements in circuit-level SEU for inverse-mode SiGe HBTs in multi-Gbps, inverse-mode digital logic.

Accurate Modeling of Single-Event Transients in a SiGe Voltage Reference Circuit

Single-event transients (SETs) are modeled in a SiGe voltage reference using compact model and full 3-D mixed-mode TCAD simulations. The effect of bias dependence and circuit loading on device-level transients is examined with regard to the voltage reference circuit. The circuit SET simulation approaches are benchmarked against measured data to assess their effectiveness in accurate modeling of SET in SiGe analog circuits. The mechanisms driving the SET of this voltage reference are then identified for the first time and traced back to the original device transients. These results enable the differences between the simulation results to be explained, providing new insight into best practices for the modeling circuit SET in different circuit topologies and device technologies.

Compact Modeling of the Temperature Dependence of Parasitic Resistances in SiGe HBTs Down to 30 K

In this paper, we investigate the physics and modeling of temperature dependence of various parasitic resistances in SiGe heterojunction bipolar transistors down to 30 K. Carrier freezeout is shown to be the dominant contributor to increased resistances at cryogenic temperatures for lightly-doped and moderately-doped regions, whereas the temperature dependence of the mobility is the dominant contributor to the temperature dependence of heavily-doped regions. Two incomplete ionization models, the classic model with a doping dependent activation energy and the recent model of Altermatt , are shown to underestimate and overestimate incomplete ionization rate below 100 K for intrinsic base doping, respectively. Analysis of experimental data shows that the bound state fraction factor is temperature dependent and including this temperature dependence enables compact modeling of resistances from 30 to 300 K for moderately-doped regions. For heavily-doped regions, a dual power law mobility approximation with complete ionization is shown to work well down to 30 K. An alternative approach is also presented for heavily-doped resistors which allows one to use the same model equation for all regions.

Evaluating the Influence of Various Body-Contacting Schemes on Single Event Transients in 45-nm SOI CMOS

We investigate the single-event transient (SET) response of T-body and notched-body contacted MOSFETs from a commercial 45 nm SOI RF-CMOS technology. Although body-contacted devices suffer from reduced RF performance compared to floating body devices, previous work on 65 nm and 90 nm MOSFETs has shown that the presence of a body-contact significantly mitigates the total ionizing dose (TID) sensitivity that is exhibited in floating-body SOI MOSFETs. The influence of body-contacting schemes on the single-event effect (SEE) sensitivity is examined here through time-resolved measurements of laser and microbeam-induced transients from T-body and notched-body MOSFETs. Laser-induced transients demonstrate the reduced SEE sensitivity of the notched-body MOSFETs as compared to the T-body MOSFETs; this is evidenced by a uniform reduction in the peak transient magnitudes and collected charge for transients captured at the worst-case bias of VDS = 1.0 V, as well as with all terminals grounded. Microbeam-induced transient data are also presented to support the validity of the laser-induced transient data. Together, these data provide new insight into the RF versus TID versus SEE tradeoffs associated with body contacting schemes in nm-scale MOSFETs, an important concern for emerging space-based electronics applications.

An Investigation of Single Event Transient Response in 45-nm and 32-nm SOI RF-CMOS Devices and Circuits

This paper uses charge deposition by two-photon absorption to present the first investigation of the physical mechanisms underlying the single event transient (SET) response of cascode structures in a 45-nm RF-CMOS/SOI technology, provides the first experimental comparison of SET between 45-nm and 32-nm RF-CMOS/SOI devices, and presents implications for circuit design in both technologies. This work leverages a number of different device types and is supported by calibrated TCAD simulations.