Ashraf A. Osman

A simple subcircuit extension of the BSIM3v3 model for CMOS RF design

An accurate and simple lumped-element extension of the BSIM3v3 MOSFET model for small-signal radio-frequency circuit simulation is proposed and investigated. Detailed comparisons of the small-signal y and s parameters with both two-dimensional device simulations and measurement data are presented. A procedure is developed to extract the values of two lumped resistors-the only added elements. The non-quasi-static and substrate effects can be modeled with these two resistors to significantly improve the model accuracy up to a frequency of 10 GHz, which is about 70% of the f/sub T/ of the 0.5 /spl mu/m NMOS transistor.

Zero-temperature-coefficient biasing point of partially depleted SOI MOSFET's

Experimental and analytical results of the front gate bias (V/sub GS/) and the drain current (I/sub DS/) with the drain voltage (V/sub DS/) of partially depleted (PD) SOI MOSFET at the Zero-Temperature-Coefficient (ZTC) point over a very wide temperature range (25-300/spl deg/C) are presented. Two distinct ZTC points are identified, one in the linear region and the other is in the saturation region. Additionally, the analysis takes into consideration the body effects, and mobility degradation with applied front gate bias. The analysis results are in excellent agreement with the experimental results. >

Comments on "A small-signal MOSFET model for radio frequency IC applications"

For original paper see E. Abou-Allam and T. Manku, ibid., vol.16, pp.437-47 (1997). A comparison is provided between the recent small-signal analysis for the distributed gate resistance in MOSFETs at RF frequencies and the lumped-element model of an earlier publication for various CMOS technologies. An improved lumped-element model is also proposed. It is demonstrated that simplified lumped-element circuits are adequate for modeling the effect of distributed gate resistance on both the y parameters and the thermal noise.

Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects

Abstract A simple analytical threshold voltage model for short-channel fully depleted SOI MOSFETs has been derived. The model is based on the analytical solution of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poissons equation and the short-channel solution to the Laplace equation, and the solution of the Poissons equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage range are determined upon which the surface potential at the buried oxide-substrate interface is accumulated, depleted, or inverted. The short-channel associated drain induced barrier lowering effects are also included in the model. The model predications are in close agreement with PISCES simulation results. The equivalence between the present model and previously reported models is proven. The proposed model is suitable for use in circuit simulation tools such as Spice.

Investigation of high temperature effects on MOSFET transconductance (g/sub m/)

High temperature effects on CMOS transconductance (g/sub m/) are investigated in linear and saturation regions. Measured g/sub m/ in the saturation region at temperatures between 27-200/spl deg/C were observed to intersect at one gate bias point. However, no such point was observed in the linear region. Similar characteristics was produced using analytical MOSFET current model that incorporate temperature dependence of device parameters.

An extended Tanh law MOSFET model for high temperature circuit simulation

The Tanh law MOSFET model proposed earlier by Shousha & Aboulwafa (see ibid., vol. 28, no. 2, p. 176-9, 1993) is extended to predict the temperature dependence of the drain current by including the temperature dependence of the threshold voltage and the mobility. The model requires fewer temperature dependent parameters compared to SPICE level2 model. The extended model shows good agreement between measurement and simulation of devices with different device geometries over wide temperature range (27-200/spl deg/C). >

A simple method to determine the floating-body voltage of SOI CMOS devices

A technique to extract the off-state floating-body (FB) voltage of silicon-on-insulator (SOI) CMOS devices is presented. The bias dependent S-parameter measurements of a single standard FB SOI device and its equivalent circuit, along with the capacitance-voltage (C-V) measurements between the drain and source of the same device, are used to determine the FB voltage. No special test structure design is needed. The technique proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depicted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage.

BSIM3 MOSFET model accuracy for RF circuit simulation

The accuracy of the BSIM3 MOSFET model for small-signal RF circuit simulation has been investigated for a 0.5 /spl mu/m CMOS process. Comparisons of the small signal y and s parameters for different bias conditions and channel lengths show that BSIM3 is reasonably well suited for small-signal analyses from 100 kHz up to 10 GHz.

Determination and assessment of the floating-body voltage of SOI CMOS devices

A self-consistent method to extract the off-state floating-body (FB) voltage of SOI CMOS devices is presented. The technique is simple and is based on CV and S-parameter measurements of a single standard SOI MOSFET device; no special test structure design is needed. The bias dependent S-parameter measurements of the FB SOI device and its equivalent circuit, along with the CV measurements between the drain and source of the same device, are used to determine the FB voltage. The technique provides reasonable insight on device off-state and leakage performances that are important for digital applications. Additionally, it proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depleted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage, demonstrating the importance of understanding FB effects on device off-state and junction leakage performances.

MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model

A modified Berkeley short-channel IGFET model (BSIM1) has been developed to accurately model the I-V characteristics and circuit performance of deep submicron MOSFET devices. The improved model provides a simple and more efficient parameter acquisition procedure for MOSFET global modeling in comparison to the original BSIM1 model. The procedure for extracting the global geometry scalable model parameters is described. The extraction procedure provides a decoupling between DC and AC modeling resulting in more accurate time-domain circuit simulations. The proposed modeling procedure eliminates the negative conductance problem experienced in the original BSIM1. The validity of the model is supported by comparisons between measured and simulated results. The focus of this paper is on the digital applications of the BSIM1 SPICE model.