Toru Shiomi

A 500 MHz pipelined burst SRAM with improved SER immunity

One of the components key to increased mobile computer performance is level-2 (L2) cache memory, which is usually a high-frequency synchronous SRAM and typically consumes >2 W. This SRAM has to be housed in low-thermal-resistance package such as the plastic ball grid array (PBGA). Power dissipation must be reduced, since battery life is prolonged and a lower-cost TQFP package can be used. In addition, cosmic-ray-induced single soft errors are becoming a problem, since memory cell node capacitance is reduced with reduction of memory cell size. At high altitude (air flight level of 30000 ft), cosmic-ray-induced SER is increased by 2 orders of magnitude. This type of soft error is significant for mobile applications. The 64k x 36 synchronous pipelined burst SRAM (PBSRAM) described has lower power and improved SER immunity.

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

A 7-Mb BiCMOS ECL (emitter coupled logic) SRAM was fabricated in a 0.8 mu m BiCMOS process. An improved buffer with a high-level output of nearly V/sub CC/ is adopted to eliminate the DC current in the level converter circuit, and the PMOS transistor has a wide operating margin in the level converter. The configurable bit organization is realized by using a sense-amplifier switch circuit with no access degradation. A wired-OR demultiplexer for the *1 output, having the same critical path as the *4 output circuit, allows for the same access time between the two modes. The *1 or *4 mode is electrically selected by the external signal. A simplified programming redundancy technology, shift redundancy, is utilized. Address programming is performed by cutting only one fuse in the shift redundancy. The RAM operates at the ECL-10K level with an access time of 7 ns. and the power dissipation at 50 MHz is 600 mW for the * mode. >

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture

Presents a new bit line architecture named T-shaped bit line architecture (TSBA), which is suitable for high speed, high density, and/or large bit-wide configuration SRAMs. TSBA, utilizing orthogonal complimentary bit lines in parallel with the word lines, is the solution to bit line pitch constraint for direct bipolar column sensing. This TSBA is applied to a 256-Kb SRAM with a typical access time of 5.8 ns. To achieve access times below 6 ns, this SRAM employs a bipolar Darlington column sense amplifier, a hierarchical column decoding scheme, a data bus shielding layout combined with TSBA, and a 0.8- mu m BiCMOS technology. >

A macro analysis of soft errors in static RAMs

In the soft error phenomenon in static RAMs (SRAMs), the mechanism of data upset is more complicated than in dynamic RAMs (DRAMs) because the storage nodes in the memory cells are connected to the power supply via load element. Therefore the critical charge has been evaluated only by computer simulation. The charge which is supplied via load element is estimated analytically, assuming alpha -particle-induced current being constant. The charge which is fed through the load element contributes to the increase of the critical charge in a 1-kbit emitter-coupled logic (ECL) RAM with a 10-k Omega resistor load. In ECL RAMs or MOS SRAMs with a larger resistor, the contribution of the charge which is fed through the load element is hardly expected, and the critical change in such RAMs is evaluated by the stored charge like DRAMs. >

New bit line architecture for ultra high speed SRAMs-T-shaped bit line and its real application to 256 k BiCMOS TTL SRAM

The authors propose a novel bit line architecture, the T-shaped bit line architecture (TSBA), which is suitable for high-speed, high-density and/or large bit-wide configuration SRAMs (static random-access memories). This architecture is applied to 256-kb BiCMOS TTL (transistor-transistor logic) I/O SRAM with a typical access time of 5.8 ns. To achieve sub-6-ns access time, a bipolar Darlington column sense amplifier, a global column decode technique, a shielded data bus technique with TSBA, and 0.8- mu m BiCMOS technology are employed.<<ETX>>

A double-word-line structure in bipolar ECL random access memory

A double-word-line structure to improve the soft error rate in a bipolar ECL RAM that has resistor-loaded and Schottky-barrier-diode (SBD) clamped memory cells is proposed. The resistor in the memory cell is connected to the first word line and the SBD to the second one, whereas both are connected to one word line in the conventional structure. The potential drop between the two word lines causes shifts of SBD clamp potential in unselected cells, and results in large potential difference in the data storage-node pairs and high soft-error immunity. The soft-error rate of the 4-kb RAM with the double-word-line structure is decreased to 1/100 of that of the conventional one, retaining an access time of 5.5 ns and minimum write-pulse width of 2.4 ns. The improvement does not accompany any degradation in electrical characteristics such as access time and write-pulse width.