Malgorzata Jurczak

Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

A new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping. The dielectric pockets have been implanted into 0.15-/spl mu/m PMOS devices showing substantial efficiency in reducing SCE and I/sub OFF/ current without altering the current drive. The dielectric pockets thus embody the ideal pocket architecture.

Self-consistent Optimization and Performance Analysis of Double-Gate MOS Transistors

The influence of architecture parameters on the charge carrier concentration has been theoretically investigated in both p-channel and n-channel Double Gate MOSFET’s. Based on a self-consistent solving of the Schrödinger and Poisson equations, this work clearly shows and quantifies the importance of the silicon thin-film thickness for electrical performance optimization of the device.

High performance 0.1 um pMOSFETs with optimized poly-Si and poly-SiGe gates

In this paper, we demonstrate that a careful optimization of poly-Si and polySiGe gates is able to extend these materials validity, thus postponing the need for metal gate. Improving dopant drive-in and interfacial distribution with fine-grain columnar poly-Si or increasing interfacial activation with poly-SiGe drastically reduces gate poly depletion and helps in suppressing B penetration. Using these options, we show highly performant 0.12 and 0.10 μm pMOS at 1.5V and 1.2V, with drive current as high as 350 μA/μm for IOFF=1 nA/μm and 300μA/μm for IOFF=25 nA/μm, respectively.