Bart Swinnen

3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias

Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other with Cu-Cu thermo-compression bonding technology, the paper demonstrate yielding 10k through-wafer 3D-via chains with a via pitch of 10μm for a via diameter of 5μm. The bonded contacts exhibit shear strengths exceeding 40MPa. Measurements indicate there is no significant contact resistance at the Cu-Cu bonded interface: within measurement accuracy, the 4-point via chain resistance is consistent with bulk Cu resistivity

The phenotypic variability of amyotrophic lateral sclerosis

Classic textbook neurology teaches that amyotrophic lateral sclerosis (ALS) is a degenerative disease that selectively affects upper and lower motor neurons and is fatal 3–5 years after onset—a description which suggests that the clinical presentation of ALS is very homogenous. However, clinical and postmortem observations, as well as genetic studies, demonstrate that there is considerable variability in the phenotypic expression of ALS. Here, we review the phenotypic variability of ALS and how it is reflected in familial and sporadic ALS, in the degree of upper and lower motor neuron involvement, in motor and extramotor involvement, and in the spectrum of ALS and frontotemporal dementia. Furthermore, we discuss some unusual clinical characteristics regarding presentation, age at onset and disease progression. Finally, we address the importance of this variability for understanding the pathogenesis of ALS and for the development of therapeutic strategies.

3D stacked IC demonstration using a through Silicon Via First approach

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13 mum CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Through-silicon via and die stacking technologies for microsystems-integration

The highest integration density of microsystems can be obtained using a 3D-stacking approach, where each layer of the stack is realized using a different technology, which may include sensors, imagers, rf and MEMS technologies. A key challenge is however to perform such stacking in a cost-effective manner. In this paper, a novel 3D TSV and 3D stacking technologies will be presented. Application examples are MEMS packaging and heterogeneous integration of imaging devices.

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot

It is widely acknowledged that three-dimensional (3-D) technologies offer numerous opportunities for system design. In recent years, significant progress has been made on these 3-D technologies, and they have become probably the best hope for carrying the semiconductor industry beyond the path of Moores law. However, a clear roadmap is missing to successfully introduce this 3-D technology onto the market. Today, a plurality of 3-D technology options exists, which requires different design and test strategies. To crystallize the many technology options in a few mainstream technologies, it is mandatory to coexplore both technology and design options. The contribution of this paper is to introduce a novel path finding methodology to untangle the many intertwined design/technology options. This holistic approach will be applied on a representative 3-D case study. Initial results demonstrate the benefits of the proposed path-finding methodology to steer the technology development and fine-tune design strategies.

Mechanical reliability of Au and Cu wire bonds to Al, Ni/Au and Ni/Pd/Au capped Cu bond pads

This work is an assessment of the mechanical reliability of Au and Cu ball bonds to Al, Ni/Au and Ni/Pd/Au surfaces in terms of high temperature storage. All systems show very good shear strength after thermal storage for up to 120 days at 150 °C. The Au ball bonds on Al surface show Kirkendall voiding starting from 60 days. This did not decrease their mechanical strength but it is expected to become a reliability issue in the long run. The Cu wire bonds on Al caps show a higher initial strength, much slower intermetallics formation and no Kirkendall voiding. This makes them a potentially better industrial solution. Excellent bond strength was found for Cu- and Au-bonds on Ni/Au and Ni/Pd/Au caps. No intermetallics formation or other microstructural change have been found on these interfaces up to 120 days at 150 °C, which was related to the full solubility of the materials along these interfaces. This result suggests that they can be a successful industrial solution for the next generation of packages.

Impact of 3D design choices on manufacturing cost

The available options in 3D IC design and manufacturing have different impact on the cost of a 3D System-on-Chip. Using the 3D cost model developed at IMEC, the cost of different system integration options is analyzed and the cost effectiveness of different technology solutions is demonstrated. The cost model is based on the IMEC 3D integration process flows and includes the cost of manufacturing equipment, fabrication facilities, personnel, and materials. Using the IMEC 3D cost model, the cost of various 3D stacking strategies is compared to single die (i.e. 2D) integration. In addition, the effect on cost of different Through-Silicon-Via (TSV) manufacturing technologies is evaluated. The effectiveness of different 3D testing strategies and their impact on system cost is also investigated.

3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding

In this paper we demonstrate functional 3D circuits obtained by a 3D Stacked IC approach using both Cu Through Silicon Vias (TSV) First and cost effective solution Die-to-Wafer Hybrid Collective bonding. The Cu TSV-First process is inserted between contact and M1. The top die is thinned down to 25µm and bonded to the landing wafer by Hybrid Bonding. Measurements and simulations of the power delay trade-offs of various 3D Ring Oscillator are provided as a demonstration of the relevance of such process route and of the design/simulation capabilities.

3D System Integration Technologies

3D technologies hold the promise to further enable increased system performance in a time where scaling has become increasingly challenging. However, 3D technologies will need to be tailored to the needs of the application they will serve. This paper describes different 3D integration schemes that are currently investigated at IMEC.