Aytac Atac

A 2.4-GHz low power high performance frequency synthesizer based on current-reuse VCO and symmetric charge pump

This paper presents a low power high performance frequency synthesizer. Based on the current-reuse VCO architecture, the whole system power consumption is significantly saved with excellent phase noise performance. Imbalance amplitude problems caused by the unsymmetrical VCO are solved by the pre-tuning mechanism, which automatically chooses the correct frequency band for the certain frequency channel. Besides, the symmetric charge pump (CP) can minimize the current mismatches and phase offset. The frequency synthesizer is fully integrated in 130-nm CMOS technology consuming 5.8 mW. Measurement results show performance of -130 dBc/Hz at 1 MHz offset phase noise, 450 fs rms jitter. The reference spur is below -75dB, and it operates successfully with 1Mbps GFSK signals as the two-point modulated transmitter.

A Multi-Frequency Multi-Standard Wideband Fractional-

This paper presents a wideband fractional- N frequency synthesizer design with a low-effort adaptive calibration technique for ΣΔ quantization noise cancellation. After adopting from the classical single-ended loop filter structure, this least mean square algorithm based calibration technique can precisely and efficiently adjust the noise cancellation digital-analog convertor current with high linearity and immunity. Besides, as long as the desired current is achieved, the calibration circuits are turned off and disconnected to save the power consumption and isolate from the signal paths. With the proposed phase-noise cancellation technique, small area and low power circuit design are achieved, meanwhile the fractional and reference spurs are highly attenuated, allowing the wideband direct frequency/phase modulation with high data rates. With low effort modification, it can be directly implemented as straightforward phase-noise enhancement for any wideband phase-locked loop applications.

{ N}

A low Power LNA for application in bluetooth low energy (BLE) receiver front-end in UMC 130-nm CMOS is presented. A capacitor cross-coupled common-gate LNA has been implemented. Due to the very low current consumption (1 mA @ 1.2 V) of the designed LNA, the standard deviation of the noise figure from the LNA circuit is dominated by process and mismatch. In this work, the reduction of standard deviation of the noise figure is achieved. The designed LNA achieves a noise figure of 3.2 dB and a voltage gain above 20 dB at all the bluetooth specified frequency ranges (2.4-2.483 GHz). The noise figure measurement with the whole receiver chain is done. The LNA fulfills the bluetooth system specifications and the measured power consumption is below 1.2 mW.

PLL With Adaptive Phase-Noise Cancellation for Low-Power Short-Range Standards

This paper presents a novel continuous time ΔΣ modulator for multi-mode operation. The design is targeted for low power, low IF multi-mode receivers and could operate on any bandwidth ranging from 0.5MHz to 1.5MHz while using the same architecture. A 3rd order, quadrature bandpass (QBP) modulator is preferred that operates on a single side of the frequency spectrum and hence improves the noise shaping characteristic. Weighted capacitive feedforward (WCFF) method is developed and analyzed to achieve the required bandwidths and IF for multi-mode operation. The achieved SNR values are 68.7/60.6/50.4dB for 0.5/1/1.5MHz bandwidths respectively, while consuming a total average current of 1.8mA from a 1.2V supply. The design is simulated with UMC 0.13μm technology.

A low power LNA for bluetooth low energy application with consideration of process and mismatch

A low complexity low power transmitter architecture for narrow band applications is presented, consisting of two single polar transmitters for the 900MHz and the 2.4GHz band, respectively. Only a single 1.8GHz local oscillator signal is used employing self-upmixing for the 2.4 GHz output. The transmitter supports arbitrary IQ modulation schemes and OFDM to fulfill the Bluetooth 4.0 “Smart”, IEEE 802.15.4/Zigbee, IEEE 802.15.4g “SUN” (Smart Metering Utility Networks), and IEEE 802.11ah Sub-GHz WLAN standards. Special emphasis is placed on keeping the digital signal processing power efficient while preserving enough flexibility to fulfill all mentioned standards. The low complexity polar transmitter frontends are also described in detail. The intended output power is 24dBm for the lower band and 13dBm for the upper band to achieve high ranges even without additional external power amplifiers. The transmitter is used in a system-on-a-chip RF transceiver for smart utility networks and the internet of things. It has been fabricated in a 130-nm CMOS technology.

A variable bandwidth & IF, continuous time ΔΣ modulator for low power low-IF receivers

This paper presents a fully integrated bluetooth low energy (BTLE) receiver front-end implemented in 0.13 um CMOS including the low noise amplifier (LNA), mixer and a variable bandwidth complex bandpass filter. The measured current consumption of the complete front-end is only 2.7 mA at 1.2 V. The designed front-end provides a voltage gain of 40 dB, a noise figure of 11 dB and a IIP3 of -21.2 dBm. The receiver front-end supports also the standard mode of bluetooth (BT) which can be easily achieved by adjusting the bandwidth of the baseband filter. Moreover, circuit techniques have been implemented in the RF front-end to improve the overall production yield and minimize production cost.

A low complexity multi standard dual band CMOS polar transmitter for smart utility networks

This paper presents a fully differential low power operational amplifier (opamp) with a variable gain bandwidth (GBW) product, ranging from 60MHz to 2GHz. The design is targeted for the filter design of continuous time wide band multi-mode ΔΣ ADCs and variable baseband filters within the low power multi-standard receivers. For the first time in literature, the offered opamp achieves 5 different GBW products 66/131/578/1080/2040MHz when loaded with high capacitive loads of 8/4/2/2/1pF differentially and by only consuming 260/410/790/1500/1900μA respectively from a 1.2V supply. The achieved figure of merit (FOM) performance is 2-3 times better than the state of the art opamps while offering a very wide GBW tuning range from 60MHz to 2GHz. The achieved performance results are given after post layout and Monte Carlo simulations, by using UMC 130nm CMOS technology.

A 1.2V, 2.7mA receiver front-end for bluetooth low energy applications

A very low power differential opamp operating in subthreshold region is proposed. The presented architecture achieves 8MHz gain-bandwidth and 20V/µsec slew rate with 5pF load while consuming a total power of 36 µW. Full voltage swing is obtained at the output by using a push-pull stage. The opamp aims to extend the application of very low power subthreshold opamps to moderate bandwidth, continuous time ΔΣ modulators by enhancing the gain-bandwidth product and improving the slew rate performance. The design is simulated with 0.13µm CMOS process, and operates with 1.2V supply voltage.

A low power variable GBW opamp from 60MHz to 2GHz for multi-standard receivers

This work presents a low complexity dual band wireless narrowband transceiver with integrated PAs. The digital-centric transceiver is suitable for IEEE 802.15.4 (ZigBee etc.), 802.15.4g SUN, Bluetooth, especially Bluetooth Low Energy and the upcoming 802.11ah sub-GHz WLAN, to enable future internet-of-things applications. The output power for the low band (800 to 960MHz) is 24.7dBm at 53.9% efficiency and for the high band (2.4GHz) 15.5dBm at 41.3% to allow high range applications without need of external PAs. The chip has been fabricated in a 0.13μm CMOS Technology.

A low power high GBW Fully Differential subthreshold CMOS opamp for CT ΔΣ modulators

This paper presents a continuous-time (CT) quadrature bandpass (QBP) ΔΣ ADC which is reconfigurable in terms of quantizer resolution, bandwidth (BW) and IF. It is designed for use in a low power low-IF multi-band transceiver system. In simulations the presented implementation in a 130nm RF CMOS process achieves a resolution of 10.5 bit. Additionally, a total power consumption of 2.3mW from an 1.2V supply voltage is simulated. The BW of the 3rd order QBP filter can be set to 0.5, 1.0 or 2.0MHz together with the IF. Likewise the loop quantizer is capable of single and dual-bit analog to digital conversion. Separate digital to analog converters (DAC) for both modes are used in the feedback of the ΔΣ loop. Furthermore an improved data weighted averaging (DWA) algorithm is presented to control the dual-bit DAC unity cells and cope with the DACs I/Q mismatch.