Zhimiao Chen

Hierarchical generation of pin accurate SystemC models based on RF circuit schematics

This paper presents a method to generate pin accurate SystemC models based on the RF circuit schematics, using a SKILL [1] based routine. This method addresses the verification and modeling of the analog/RF circuits in the event driven digital domain using SystemC, based on the same data base created by the circuit designer. The proposed method was employed to model a specific test case, comprising a phase locked loop in a RF receiver chain. The reliability of the SystemC models have been proven by comparing the simulation results with the Verilog-AMS(wreal) models. The pin accurate SystemC models were found to be well suited for top down design, virtual prototyping and verification in SoC implementation. Additionally, the SystemC models are very efficient regarding the simulation speed and flexibility to pass abstract data types with real numbers through the ports.

A low complexity multi standard dual band CMOS polar transmitter for smart utility networks

A low complexity low power transmitter architecture for narrow band applications is presented, consisting of two single polar transmitters for the 900MHz and the 2.4GHz band, respectively. Only a single 1.8GHz local oscillator signal is used employing self-upmixing for the 2.4 GHz output. The transmitter supports arbitrary IQ modulation schemes and OFDM to fulfill the Bluetooth 4.0 “Smart”, IEEE 802.15.4/Zigbee, IEEE 802.15.4g “SUN” (Smart Metering Utility Networks), and IEEE 802.11ah Sub-GHz WLAN standards. Special emphasis is placed on keeping the digital signal processing power efficient while preserving enough flexibility to fulfill all mentioned standards. The low complexity polar transmitter frontends are also described in detail. The intended output power is 24dBm for the lower band and 13dBm for the upper band to achieve high ranges even without additional external power amplifiers. The transmitter is used in a system-on-a-chip RF transceiver for smart utility networks and the internet of things. It has been fabricated in a 130-nm CMOS technology.

A 1.2V, 2.7mA receiver front-end for bluetooth low energy applications

This paper presents a fully integrated bluetooth low energy (BTLE) receiver front-end implemented in 0.13 um CMOS including the low noise amplifier (LNA), mixer and a variable bandwidth complex bandpass filter. The measured current consumption of the complete front-end is only 2.7 mA at 1.2 V. The designed front-end provides a voltage gain of 40 dB, a noise figure of 11 dB and a IIP3 of -21.2 dBm. The receiver front-end supports also the standard mode of bluetooth (BT) which can be easily achieved by adjusting the bandwidth of the baseband filter. Moreover, circuit techniques have been implemented in the RF front-end to improve the overall production yield and minimize production cost.

Low-effort high-performance viterbi-based receiver for Bluetooth LE applications

This paper presents a novel demodulator architecture which significantly improves the receiver performance for continuous phase modulation (CPM) signals with low-effort and low-complexity design. A Viterbi algorithm (VA) based soft decision is implemented with multiple bits differential discriminator to fully utilize the dynamical range. The whole digital circuit is verified and synthesized in ASICs, and its BER performance against channel noise is measured through FPGA with the Bluetooth receiver chip. Compared to hard-decision and decision feedback equalizer (DFE) methods, measurement results show that the proposed demodulator gains a large advantage in Bluetooth Low Energy (LE) communications where power efficiency and implementation complexity are of primary concern.

A low complexity multistandard dual band wireless transceiver with integrated 24.7dBm 54% efficiency polar PA in a 0.13μm CMOS technology

This work presents a low complexity dual band wireless narrowband transceiver with integrated PAs. The digital-centric transceiver is suitable for IEEE 802.15.4 (ZigBee etc.), 802.15.4g SUN, Bluetooth, especially Bluetooth Low Energy and the upcoming 802.11ah sub-GHz WLAN, to enable future internet-of-things applications. The output power for the low band (800 to 960MHz) is 24.7dBm at 53.9% efficiency and for the high band (2.4GHz) 15.5dBm at 41.3% to allow high range applications without need of external PAs. The chip has been fabricated in a 0.13μm CMOS Technology.

An HDL-Based System Design Methodology for Multistandard RF SoC's

Multistandard SoCs including advanced RF and analog circuitry with digital blocks are pervasive in modern ICs. However, the system design and verification methodologies that capture the complexity of multistandard RF SoCs are still limited. In this paper, an HDL design methodology is introduced for multistandard RF SoCs, which covers all the design layers from system design, to automatic extraction of the models from circuits and a systematic top level verification. The offered HDL based design methodology combines top down and bottom up design approaches, and brings the design and verification closer by reflecting the circuits to models automatically via an Automatic Parameter Extraction (APX) tool. System or block level verification is obtained with models automatically by overnight runs, without the need for extra test benches or designer interaction. This enables short term detection of functional errors or performance losses. A first time tape out of a multimode Bluetooth transceiver SoC is designed and fabricated in 8 months by using the offered methodology. The accuracy of the system level simulations show a very good match with the measurement results after fabrication. The test SoC is fabricated with 0.13 μm CMOS technology.

Comparison of modeling approaches through hierarchical behavioral modeling of a GNSS receiver front-end

This paper analyzes and compares the mixed-signal modeling approaches (conservative, timed data flow, and event-driven, as well as the baseband modeling approach) through the hierarchical behavioral modeling of a GNSS (Global Navigation Satellite System) receiver front-end. Based on the result of the comparison, one hierarchical modeling flow is finally derived comprising multi-modeling approaches with reduced manual modeling effort.

Gain and noise optimization of a passive sliding IF architecture

This paper presents gain and noise optimization of a passive Sliding IF downconverter as a promising choice for Zero-IF and Low-IF receivers. With detailed mathematical analysis of the architecture we propose a new design that provides 7.6 dB improvement of relative conversion gain with profound noise figure and IIP3 performance. The results of the mathematical derivation are supported by modeling, circuit simulation and measurement of a prototype chip fabricated on a standard 130nm CMOS technology. The chip operates under supply voltage of 1.2V and occupies 750μm × 200μm active area.

A mixed-domain modeling method for RF systems

This paper introduces a mixed domain event-driven modeling method for RF systems. The circuit behaviors are modeled in time/frequency domain adaptively combining with the equivalent baseband representation of each spectral component. Comparing to traditional baseband modeling methods or harmonic balance simulation techniques, this mixed domain method loose the requirements of relations among carrier frequencies of spectral components, and therefore can be widely used in mixed-signal circuit modeling. Furthermore, this method brings in a great simulation speed up over the simulation in passband signal abstraction, while the modeling accuracy can be guaranteed to meet the requirements of functional verifications.

A SystemC Virtual Prototyping based Methodology for Multi-Standard SoC Functional Verification

This paper describes a functional verification methodology for multi-standard wireless Systems-on-Chip (SoC) based on SystemC Virtual Prototyping (VP). The proposed semi-automatic pin-accurate RF VP generation method reduces huge handcrafting work to abstract circuitry into the event-driven simulation domain with satisfactory accuracy, while enabling the flexibility to choose different abstraction levels. A seamless transition between various signal abstractions is enabled by operator overload, e.g. passband and equivalent baseband in order to minimize simulation time according to test cases. This methodology is demonstrated for a low power RF transceiver with the achieved simulation speed of 500μs in 10s computation time.