Bastian Mohr

An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS

This paper presents an RFDAC based transmitter for wireless mobile and connectivity applications in a 65 nm CMOS technology. The transmitter RFDAC has a segmented architecture employing 4 LSB and 16 MSB unit cells for each I and Q path, thus providing a resolution of 8 bit + signum. Switchable LO drivers and unit cells with current shutdown are used to reduce power dissipation when transmitting signals with high PAPR such as IEEE 802.11 (WLAN) or 3GPP Long Term Evolution (LTE). The frontend is capable of transmitting an 64 QAM-OFDM WLAN signal at a center frequency of 1 GHz with an output power of -8 dBm and an EVM of 4.66 %. Analog power dissipation is 34 mW, clock and LO divider use less than 10 mW, and the digital block consumes about 87 mW. The area of the frontend is about 0.4 mm2.

12.4 A 7.5W-output-power 96%-efficiency capacitor-free single-inductor 4-channel all-digital integrated DC-DC LED driver in a 0.18μm technology

Todays general lighting development is driven by improvements in semiconductor-based systems. It is expected that solid-state lighting (SSL) will dominate general lighting in the near future. Two main challenges that must be met in SSL are the reduction of the bill of materials (BOM), and an increase in functionality. In [1], a floating DC-DC buck controller is presented. This controller adds to the BOM, as every device of the power path is discrete and the ASIC can only drive a single LED string. In contrast to that, [2] offers a high-current fully integrated power stage. However, several external passives are introduced and the technology inhibits stacking multiple LEDs for high luminous efficacy. To overcome this, [3] presents an integrated HV power path with only the inductor as an external component. Ina parallel development, [4] reports an LED driver similar to [3], but that uses a discrete Schottky diode for asynchronous rectification. In fact, [1-4] demonstrate single output LED drivers without additional functionality or full color spectrum. To overcome these drawbacks in light spectrum and control, [5] presents a 3-channel LED driver. However, the external passives are numerous, which significantly impairs the overall BOM.

A 2.4-GHz low power high performance frequency synthesizer based on current-reuse VCO and symmetric charge pump

This paper presents a low power high performance frequency synthesizer. Based on the current-reuse VCO architecture, the whole system power consumption is significantly saved with excellent phase noise performance. Imbalance amplitude problems caused by the unsymmetrical VCO are solved by the pre-tuning mechanism, which automatically chooses the correct frequency band for the certain frequency channel. Besides, the symmetric charge pump (CP) can minimize the current mismatches and phase offset. The frequency synthesizer is fully integrated in 130-nm CMOS technology consuming 5.8 mW. Measurement results show performance of -130 dBc/Hz at 1 MHz offset phase noise, 450 fs rms jitter. The reference spur is below -75dB, and it operates successfully with 1Mbps GFSK signals as the two-point modulated transmitter.

A Multi-Frequency Multi-Standard Wideband Fractional-

This paper presents a wideband fractional- N frequency synthesizer design with a low-effort adaptive calibration technique for ΣΔ quantization noise cancellation. After adopting from the classical single-ended loop filter structure, this least mean square algorithm based calibration technique can precisely and efficiently adjust the noise cancellation digital-analog convertor current with high linearity and immunity. Besides, as long as the desired current is achieved, the calibration circuits are turned off and disconnected to save the power consumption and isolate from the signal paths. With the proposed phase-noise cancellation technique, small area and low power circuit design are achieved, meanwhile the fractional and reference spurs are highly attenuated, allowing the wideband direct frequency/phase modulation with high data rates. With low effort modification, it can be directly implemented as straightforward phase-noise enhancement for any wideband phase-locked loop applications.

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This paper presents a novel multi-standard digital low-IF receiver, which provides low-power low-complexity, flexible and robust performance for short distance communication applications. Over the various incoming data rates and carrier frequencies, the corresponding symbol timing is recovered by the ΣΔ modulated frequency divider from fractional-N synthesizer, and the carrier frequency offset is calibrated by direct digital synthesizer generated intermediate frequency. The proposed digital receiver is fully integrated with 130 nm CMOS technology, occupying 0.83 mm2 area with 4.5 mW. Through the verification in an FPGA, the measurement results show a great potential in flexible and cost oriented applications.

PLL With Adaptive Phase-Noise Cancellation for Low-Power Short-Range Standards

This work presents an analysis of digital predistortion (DPD) architectures for radio-frequency digital-to-analog convertor (RFDAC) based direct digital to RF transmitter (DRF). The nonlinearity of the DRF frontend is determined by circuit simulation. Direct learning and indirect learning structures using least mean square (LMS) and normalized LMS (NLMS) estimation algorithm are evaluated with respect to the lowest normalized mean square error (NMSE) and the error vector magnitude (EVM) and spectral emissions when processing broadband OFDM based IEEE 802.11a (WLAN) signals. MATLAB simulations show the possibility to reduce out-of-band emissions by 8 dB and to improve the EVM from 4.27% without predistortion to 2.50%using DPD. All DPDs show similar results, hence the architecture with the lowest complexity is evaluated for digital implementation. The impact of quantization and delay is evaluated, increasing the EVM to 3.71% and showing a strong dependence of the resulting EVM from digital circuit delay.

A Low-Power Low-Complexity Multi-Standard Digital Receiver for Joint Clock Recovery and Carrier Frequency Offset Calibration

A low complexity low power transmitter architecture for narrow band applications is presented, consisting of two single polar transmitters for the 900MHz and the 2.4GHz band, respectively. Only a single 1.8GHz local oscillator signal is used employing self-upmixing for the 2.4 GHz output. The transmitter supports arbitrary IQ modulation schemes and OFDM to fulfill the Bluetooth 4.0 “Smart”, IEEE 802.15.4/Zigbee, IEEE 802.15.4g “SUN” (Smart Metering Utility Networks), and IEEE 802.11ah Sub-GHz WLAN standards. Special emphasis is placed on keeping the digital signal processing power efficient while preserving enough flexibility to fulfill all mentioned standards. The low complexity polar transmitter frontends are also described in detail. The intended output power is 24dBm for the lower band and 13dBm for the upper band to achieve high ranges even without additional external power amplifiers. The transmitter is used in a system-on-a-chip RF transceiver for smart utility networks and the internet of things. It has been fabricated in a 130-nm CMOS technology.

Analysis of digital predistortion architectures for direct digital-to-RF transmitter systems

This paper presents a digital centric transmitter architecture with clock domain transition from the baseband clock to a clock derived from the local oscillator of the proposed transmitter. Both clock domains are asynchronous and variable in general, hence this transistion block represents the key building block of the digital signal processing chain. It consists of a synchronizing stage, a timing control unit, and a modified Generalized Farrow upsample filter which allows to implement further upsample stages using simple integer-ratio CIC filters. The architecture is well appropriate for low energy digital-centric hardware designs. Highly reconfigurable, it is applied in a state-of-the-art multimode multistandard transmitter with radio frequency DAC frontend, suitable for WLAN, UMTS, LTE and other recent standards.

A low complexity multi standard dual band CMOS polar transmitter for smart utility networks

This work presents an element selection logic (ESL) for a radio frequency digital to analog converter (RF-DAC) based multistandard transmitter in 65 nm CMOS. After introducing the transmitter system and the basics of mismatch shaping, the ESL is applied to an OFDM transmitter. The design is optimized with respect to the signal properties and synthesis is done for the mentioned CMOS technology. Simulation results show a significant improvement of the signal quality in the desired band.

A digital centric transmitter architecture with arbitrary ratio baseband-to-LO upsampling

This work presents a low complexity dual band wireless narrowband transceiver with integrated PAs. The digital-centric transceiver is suitable for IEEE 802.15.4 (ZigBee etc.), 802.15.4g SUN, Bluetooth, especially Bluetooth Low Energy and the upcoming 802.11ah sub-GHz WLAN, to enable future internet-of-things applications. The output power for the low band (800 to 960MHz) is 24.7dBm at 53.9% efficiency and for the high band (2.4GHz) 15.5dBm at 41.3% to allow high range applications without need of external PAs. The chip has been fabricated in a 0.13μm CMOS Technology.