Azeez Bhavnagarwala

Fluctuation limits & scaling opportunities for CMOS SRAM cells

Fundamental limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring the local stochastic distributions of read, write and retention DC margins of 65nm PDSOI CMOS SRAM cells. DC measurements show, for the first time, the write operation to be more fluctuation limited. Measurements also reveal fundamental insights into terminal voltage dependencies of the fluctuations of cell storage node voltages - observations that are engaged to increase cell immunity to fluctuations by several orders of magnitude by biasing the cell terminal voltages appropriately

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

Fluctuation limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring local stochastic distributions of 65-nm PDSOI CMOS SRAM cell storage node voltages during read, write, and retention modes of operation. These measurements reveal insights into terminal voltage dependencies of cell margin distributions - observations that are engaged to increase cell immunity to random VT fluctuations by several orders of magnitude by biasing the cell terminal voltages dynamically with a read-write asymmetry. Combinations of circuit techniques implementing these dynamic cell biasing schemes are demonstrated in a 9 kb times74 b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST. Measurements demonstrate these techniques to enable VMIN reductions of over 200 mV - lowering measured VMIN to 0.54 V and 0.38 V/0.50 V for single and dual VDD implementations, respectively. The techniques consume a 10%-12% overhead in area, impact performance marginally (<5%) and also enable over 50% reduction in cell leakage.

A transregional CMOS SRAM with single, logic V/sub DD/ and dynamic power rails

New circuit techniques are reported that enable a single V/sub DD/ SRAM to operate at logic compatible voltages with a cell read current and cell static noise margin (SNM) typically seen with higher/dual V/sub DD/ SRAMs. Implemented in a 65nm CMOS SOI process with no alterations to the CMOS process or to a conventional, single V/sub T/ SRAM cell, the voltage across power rails of the selected SRAM cells self-biases to permit a higher-than-V/sub DD/ voltage during WL active periods and a lower than 2V/sub T/ voltage at all other times. Bootstrapping the cell row power supply and regulating the cell subarray virtual ground voltage enables the above Transregional SRAM operation resulting in near-subthreshold data storage and superthreshold access, lowering total leakage by over 10/spl times/ and improving I/sub READ/ and SNM by 7% and 18% respectively with a total area overhead of less than 13%.

A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing

Combinations of circuit techniques enabling tolerance to Vtau fluctuations in SRAM cell transistors during read or write operations and significant reductions in minimum operating voltage are reported. Implemented in a 9 Kb times 74 b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST, these techniques, demonstrate VMIN of 0.58 V and 0.40 V/0.54 V for single and dual VDD implementations respectively. The techniques consume a 10-12% overhead in area, improve performance marginally and also enable over 50% reduction in cell leakage with minimal circuit overhead.

Low-power circuits and technology for wireless digital systems

As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a given application. Determining this balance is crucial for battery-powered handheld devices in which transistor leakage and active power limit the available system performance. This paper explores these questions and describes circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology.

A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias

New SRAM circuit techniques implemented in a standard 0.13 /spl mu/m bulk Si CMOS process are reported in this work that (i) enable pico-joule energy dissipation per accessed bit at 1 GHz, (ii) lower total leakage power by over 80% from all unaccessed cells, during both active and standby modes, using a rigorous, self reverse biasing scheme that addresses leakage due to quantum tunneling and thermal excitation in all cell transistors, with an area, performance and noise margin penalty of less than 3% each and (iii) enable a programmable leakage reduction option that lowers leakage by over 90% when stored data is no longer desired.

Interconnect-centric array architectures for minimum SRAM access time

Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are reported. Verified to be accurate with published SRAMs, these models enable the design of optimal array architectures to minimize total access time by balancing communication distance limited wire delays with fan-out and area limited gate delays.

Scalability options for future SRAM memories

As CMOS technology approaches the limits of scaling, device dimensions become similar in magnitude to the discrete structures and components of the device itself. Random process variations quickly are becoming a major limitation to limiting manufacturing yields. The 6T-SRAM cell has become the first casualty to these scaling effects, and has increased in size relative to larger logic components in recent technology nodes. Physical and electrical modifications to the SRAM cell and peripheral circuits can provide additional tolerance and allow continued scaling into the foreseeable future. This paper examines this issue and suggests some alternative structures that have been demonstrated to provide improvements

EP2: The semiconductor industry in 2025

The historical predictability of Moores Law as a law of economics has enabled the semiconductor industry to not only achieve extraordinary innovation, but overtime has redefined how we build complex electronic systems. We have developed an eco-system of specialized entities to solve specific challenges such as Equipment Development, Foundry Services, Design, EDA, Software, and Consumer Services. While more specialization was an undisputed trend of the past, we are beginning to see hardware companies becoming less specialized - manufacturing companies entering design, design companies enter services to name a few. This change allows for larger fraction of the revenue pie to belong to one entity and perhaps even allowing for recurring revenue to a hardware company thus making economics sustainable. Before the supposed physical limits are reached, what is the right approach that will win and allow Moores Law of economics to continue its self fulfilling prophecy? More vertically integrated companies that enable recurring revenue? Or more horizontally integrated companies that focus on specialized innovation?

A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um 2 6T bitcell in a 16nm FinFET CMOS process

We propose and demonstrate in silicon simple, new circuit solutions using a standard 1-1-2 fin 0.09 um2 6T SRAM commercial bitcell in a 16nm FinFET CMOS process to enable a 400mV active VMIN, 200mV retention VMIN SRAM in a 64Kb CMOS array with 128b/BL. Active VMIN is enabled with a self-triggered feedback on an under-driven BL with faster and more robust signal development on the BL at lower voltages - providing dual read assist, and also a 2X tighter offset voltage distribution when compared to conventional differential voltage sensing. 200mV retention VMIN is enabled by reusing write assist circuit overhead while engaging two key observations: insensitivity of bitcell stability to systematic variations and sensitivity of bitcell data to noise on the power grid in the subthreshold/near threshold region. Average FMAX of 140MHz and 2.8GHz are measured across all chips for VDD at 0.4V and 0.9V respectively.